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via technologies, inc. preliminary VT6516 datasheet 1 VT6516 16/12-p ort 10/100b ase -t/tx e thernet s witch c ontroller revision ? e ? datasheet (preliminary) issue 1: july 31, 1999 via technologies, inc.
via technologies, inc. preliminary VT6516 datasheet 2 p reliminary r elease please contact via technologies for the latest documentation. copyright notice: copyright ? 1995, via technologies incorporated. printed in taiwan. a ll r ights r eserved . no part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise without the prior written permission of via technologies incorporated. the vt86c100p may only be used to identify products of via technologies. all trademarks are the properties of their respective owners. disclaimer notice: no license is granted, implied or otherwise, under any patent or patent rights of via technologies. via technologies makes no warranties, implied or otherwise, in regard to this document and to the products described in this document. the information provided by this document is believed to be accurate and reliable to the publication date of this document. however, via technologies assumes no responsibility for any errors in this document. furthermore, via technologies assumes no responsibility for the use or misuse of the information in this document and for any patent infringements that may arise from the use of this document. the information and product specifications within this document are subject to change at any time, without notice and without obligation to notify any person of such change. offices: 1045 mission court 8 th floor, no. 533 fremont, ca 94539 chung-cheng rd., hsin-tien usa taipei, taiwan roc tel: (510) 683-3300 tel: (886- 2) 2218-5452 fax: (510) 683-3301 fax: (886-2) 2218-5453 online services: bbs : 886-2-2186408 ftp : ftp.via.com.tw http: www.via.com.tw ? or- www.viatech.com
via technologies, inc. preliminary VT6516 datasheet 3 t able of c ontents t able of c ontents ................................ ................................ ................................ ................................ 3 f igures and t ables ................................ ................................ ................................ ............................... 4 r eversion h istory ................................ ................................ ................................ ................................ 5 f eatures ................................ ................................ ................................ ................................ ................ 6 b lock d iagram ................................ ................................ ................................ ................................ ...... 9 b all out d iagram ................................ ................................ ................................ ............................... 11 rmii-mode ball out diagram ................................ ................................ ................................ ........... 11 mii-mode ballout diagram ................................ ................................ ................................ ............... 12 l ogic s ymbol ................................ ................................ ................................ ................................ ...... 13 p in d escriptions ................................ ................................ ................................ ................................ .. 14 j umper s trapping ................................ ................................ ................................ ................................ . 18 section i functional descriptions ................................ ................................ ...................... 19 1. g eneral d escription ................................ ................................ ................................ ...................... 19 2. t he via e ther s witch a rchitecture ................................ ................................ ............................ 19 2.1 switch initialization procedures ................................ ................................ ................................ .. 19 2.2 packet receiving and forwarding follow ................................ ....... ??~ ! ?|??w?q??? ?c 3. i nterface d escriptions ................................ ................................ ................................ ................... 20 3.1 buffer memory (sdram) interface and table (sram) interface .. ??~ ! ?|??w?q??? ?c 4. f unctional d escription ................................ ................................ ................................ ................. 33 4.1 packet reception and address recognition ................................ ................................ .................. 33 4.2 packet forwarding and vlan ................................ ................................ ................................ ..... 33 4.3 network management features ................................ ................................ ................................ ... 34 section ii register map ................................ ................................ ................................ ............... 36 1. r egister t ables ................................ ................................ ................................ ............................. 36 2 cpu i nterface r egisters m ap ................................ ................................ ................................ ......... 36 3 s witch i nternal r egisters m ap ................................ ................................ ................................ ..... 37 4. d etail of s witch r egister ................................ ................................ ................................ .............. 44 4.1 registers of sdram control module ................................ ................................ ......................... 44 4.2 registers of sram control module ................................ ................................ ............................ 46 4.4 registers of buffer control module ................................ ................................ ............................. 48 4.5 registers of forwarding control module ................................ ................................ ................... 49 4.6 registers of phy control module ................................ ................................ .............................. 53 4.7 registers of eeprom control module ................................ ................................ ....................... 55 4.8 registers of cpu interface module ................................ ................................ ............................. 56 4.9 registers of mac/io control module ................................ ................................ ......................... 59 4.10 registers of cpu io control module ................................ ................................ ....................... 63 section iii electrical specifications ................................ ................................ ................. 65 a bsolute m aximum r atings ................................ ................................ ................................ ............... 65 dc c haracteristics ................................ ................................ ................................ ............................ 65 ac c haracteristics ................................ ................................ ................................ ............................ 65 p ackage m echanical s pecifications ................................ ................................ ................................ . 73
via technologies, inc. preliminary VT6516 datasheet 4 f igures and t ables figure 1: block diagram ................................ ................................ ............................. 9 figure 3-3 ................................ ................................ ................................ ................. 22 figure 3-6: algorithm of initialization of free link lists. ................................ .......... 22 figure 3-1 sram ................................ ................................ ................................ ...... 26 figure 3-2 free buffer link structure ................................ ................................ .......... 27 table 1-0 free buffer link structure ................................ ................................ ............ 27 figure 3-5 the address table entries structure + ................................ ........................ 27 table 1-1 address table structure ................................ ................................ .............. 28 table 3-1 rmii interface signals ................................ ................................ ................ 30 figure 3-1 rmii timing diagram ................................ ................................ ................ 30 table 3-2 mii interface signals ................................ ................................ .................. 31 figure 3-2 mii timing diagram ................................ ................................ .................. 31
via technologies, inc. preliminary VT6516 datasheet 5 r eversion h istory reversion date reason for change by v0.90 2/18/1999 first release version jeffreychang v0.91 6/2/1999 add d version silicon features modification jeffreychang v0.92 8/23/1999 add e version silicon features modification murphychen v0.93 9/9/1999 revision according to weipin ? s, kevin ? s, and ruth ? s comments murphychen
via technologies, inc. preliminary VT6516 datasheet 6 f eatures l single chip 16/12 ports 10/100m ethernet switch controller - highly integrated single chip shared memory switch engine - with option for 16 rmii (reduced media independent interface) ports or 12 mii (media independent interface) ports - non-blocking layer 2 switch, 148,810 packets/sec on each 100mbps ethernet port l media access control (mac) - dual 192-bytes fifo ? s of receive and transmit for each port - crc generator for outgoing packets from cpu port - ieee 802.3x compliant flow control for full duplex ports - backpressure for half duplex ports l two switching mechanisms - supports ? store and forward ? switching without forwarding crc-bad packets - supports ? cut through ? switching subject to long packets of length over 290 bytes for 100mbps ports or of length over 98 bytes for 10mbps ports l packet buffering - glueless 64-bit interface to sdram as a packet buffer pool with size from 2m bytes (sgram) to 512 m bytes - 1536 bytes for each packet buffer l external 32 bits ssram interface for forwarding table and memory link table - link list structure initialized by software - 2k up to 32k unicast/multicast addresses table entries with vlan information - supports static entries for upper-layer multicast protocols, e.g. igmp l advanced address recognition - layer 2 mac address recognition engine to enable wire-speed forwarding rate - self learning mechanism - supports multiple mac address per-port from 2k up to 32k unicast/multicast addresses l switch management support - supports port mirroring (sniffer feature) - supports spanning tree algorithm - supports cpu direct access to sdram and ssram - supports five statistical counters in each port l supports i 2 c eeprom interface for customized configuration l support port-grouping vlan - configurable server ports belonging to multiple vlan groups l support port-based trunking - three types of trunk grouping: one trunk group with 2 or 4 ports, two trunk groups each with 2 ports - load balance according to mac address and port number l cpu interface via 8/16 bits isa-like interface
via technologies, inc. preliminary VT6516 datasheet 7 - chip initialization, auto-aging and spanning tree algorithm support by firmware - auto-sensing 10/100m media speed, duplex mode, and flow-control capability by firmware l 50mhz internal reference clock rate l 50~100mhz sdram clock rate, typically 83mhz l 50~100mhz ssram clock rate, typically 83mhz l single +3.3v supply, 0.3 m m standard cmos technology l 476 ball bga package

via technologies, inc. preliminary VT6516 datarsheet 99/12/09 9 b lock d iagram figure 1: block diagram forwarding control buffer control scheduler queue control sram control sdram control cpu interface input control rmac output control tmac

via technologies, inc. preliminary VT6516 datarsheet 99/12/09 11 b all out d iagram rmii-mode ball out diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 a csdv2 crs.d v1 rxd1.1 txen1 txd1.0 rxd0.0 md1 md3 md5 md7 md9 md11 md45 md47 ras0 ma3 ma7 ma11 dcs2 dwe0 md49 md20 md22 md24 md57 md58 b rxd1.2 txd1.2 txd1.1 rxd0.1 csdv0 txd0.0 md32 md34 md36 md38 md40 md42 md14 cas1 ma0 ma4 ma8 ba0 dcs1 dwe1 md18 md52 md54 md56 md26 md27 c txen2 rxd0.2 txd0.2 txd0.1 txen0 rxd1.0 md0 md2 md4 md6 md8 md10 md46 cas0 ma1 ma5 ma9 ba1 dcs0 md16 md50 md21 md23 md25 md59 md28 d txd1.3 csdv3 txen3 nc nc nc md33 gnd md37 md39 md41 md43 md13 md15 ras1 ma2 ma6 ma10 dcs3 md48 md19 md53 md55 md60 md29 md61 e rxd0.3 txd0.3 rxd1.3 nc vddi gndi gnd md35 vdd vdd vdd md12 md44 gnd gnd gnd vdd vdd vdd md17 md51 gndi dclk md30 md62 md31 f rxd1.4 txd0.4 rxd0.4 txen4 rclk5 0 vddi gnd nc nc gnd gndi vddi md63 sd16 sd17 sd18 g rxd0.5 csdv4 txd1.4 txen5 vdd gnd gnd sclk sd19 sd20 sd21 sd22 h txd1.5 rxd1.5 txd0.5 nc vdd vdd nc sd23 sd24 sd25 sd26 sd27 j txd0.6 rxd0.6 csdv5 nc vdd vdd sd31 sd28 sd29 sd30 k csdv6 txd1.6 rxd1.6 txen6 nc vdd sa4 sa6 sa7 sa5 l rxd1.7 txd0.7 rxd0.7 nc gnd gnd gnd gnd gnd gnd gnd vdd sa3 sa2 sa13 sa0 m csrv7 txd1.7 txen7 nc gnd gnd gnd gnd gnd gnd gnd sa10 sa11 sa12 sa13 sa14 n rxd1.8 txd1.8 csdv8 txen8 nc gnd gnd gnd gnd gnd gnd sa15 sa16 sa17 sa9 sa8 p txd0.8 rxd0.8 csdv9 txen9 nc gnd gnd gnd gnd gnd gnd gnd sd0 sd3 sd2 sd18 r txd1.9 rxd1.9 txd0.9 nc vdd gnd gnd gnd gnd gnd gnd gnd sd4 sd7 sd6 sd5 t rxd0.9 rxd0.1 0 txd0.1 0 txen1 0 vdd gnd gnd gnd gnd gnd gnd sd11 sd12 sd10 sd9 sd8 u rxd1.1 0 txd1.1 0 csdv1 0 nc vdd vpp sads# sd15 sd14 sd13 v rxd0.1 1 txd0.1 1 rxd1.1 1 txen1 1 vdd vpp soe# scs1# scs0# swe# w txd1.1 1 csdv1 1 rxd0.1 2 txen1 2 nc gnd gnd scs3# scs2# ha0 hcs# scs4# y txd0.1 2 rxd1.1 2 txd1.1 2 nc gnd gndi gndi hclk hd15 intrq ha1 ha2 aa csdv1 2 rxd0.1 3 txd0.1 3 nc gndi vddi vdd vdd gnd gnd gnd gndi hd1 hd0 iow# ior# ab rxd1.1 3 txen1 3 txd1.1 3 nc vddi vdd vdd nc vpp vpp nc nc gnd gnd nc nc vpp vpp vpp test12 vddi gnd hd3 hd13 hd2 hd14 ac csdv1 3 csdv1 4 txd1.1 4 nc eec nc nc nc nc nc nc nc nc nc nc nc nc nc test7 test11 test16 test17 hd5 hd11 hd4 hd12 ad rxd1.1 4 txd0.1 4 rxd1.1 5 txen1 5 eeio nc nc nc nc nc nc nc nc nc nc nc nc test3 test6 test10 test15 test20 test23 hd9 hd6 hd10 ae rxd0.1 4 csdv1 5 txd0.1 5 mdc nc nc nc nc nc nc nc nc nc nc nc nc nc test2 test5 test9 test14 test19 test22 test25 hd8 hd7 af txen1 4 txd1.1 5 rxd0.1 5 mdio nc nc nc nc nc nc nc nc nc nc nc nc nc test1 test4 test8 test13 test18 test21 test24 test26 reset #
via technologies, inc. preliminary VT6516 datarsheet 99/12/09 12 mii-mode ballout diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 a crs1 rxd3_ 0 col0 txd1_ 0 rxd0_ 0 md1 md32 md34 md36 md38 md40 md42 md14 cas1# ma0 ma4 ma8 ba0 dcs1# dwe1# md18 md20 md22 md24 md57 md58 b rxd1_ 1 rxdv0 txd3_ 0 rxd2_ 0 crs0 txd0_ 0 md0 md2 md4 md6 md8 md10 md46 cas0# ma1 ma5 ma9 ba1 dcs0# md16 md50 md52 md54 md56 md26 md27 c txen1 txd1_ 1 txd0_ 1 txd2_ 0 txen0 rxd1_ 0 md33 md35 md37 md39 md41 md43 md13 md15 ras1# ma2 ma6 ma10 dcs3# md48 md19 md21 md23 md25 md59 md28 d txd3_ 1 rxd0_ 1 col1 nc nc nc md3 vss md7 md9 md11 md12 md44 ras0# ma3 ma7 ma11 dcs2# dwe0# md17 md51 md53 md55 md60 md29 md61 e rxd2_ 1 rxdv1 rxd3_ 1 nc vdd gnd vss md5 vcc vcc vcc md45 md47 vss vss vss vcc vcc vcc md49 nc gnd dclk md30 md62 md31 f rxd1_ 2 txd2_ 1 rxd0_ 2 txen2 rclk5 0 vdd vss nc nc vss gnd vdd md63 sd16 sd17 sd18 g rxd2_ 2 txd0_ 2 txd1_ 2 col2 vcc vss vss sclk sd19 sd20 sd21 sd22 h txd3_ 2 crs2 txd2_ 2 rclk2 vcc vcc nc sd23 sd24 sd25 sd26 sd27 j txd0_ 3 rxd3_ 2 rxdv2 tclk2 vcc vcc sd31 sd28 sd29 sd30 k rxd0_ 3 crs3 txd1_ 3 rxd1_ 3 txen3 vcc sa4 sa6 sa7 sa5 l rxd3_ 3 txd2_ 3 rxd2_ 3 rclk3 vss vss vss vss vss vss vss vcc sa3 sa2 sa1 sa0 m rxdv3 txd3_ 3 col3 tclk3 vss vss vss vss vss vss vss sa10 sa11 sa12 sa13 sa14 n txd0_ 4 rxd1_ 4 txd1_ 4 crs4 txen4 vss vss vss vss vss vss sa15 sa16 sa17 sa9 sa8 p txd3_ 4 rxd0_ 4 rxdv4 col4 rclk4 vss vss vss vss vss vss vss sd0 sd3 sd2 sd1 r rxd2_ 4 rxd3_ 4 txd2_ 4 tclk4 vcc vss vss vss vss vss vss vss sd4 sd7 sd6 sd5 t rxd1_ 5 rxd0_ 5 txd0_ 5 txen5 vcc vss vss vss vss vss vss sd11 sd12 sd10 sd9 sd8 u rxd2_ 5 txd1_ 5 crs5 tclk5 vcc vcc sads# sd15 sd14 sd13 v txd3_ 5 txd2_ 5 rxd3_ 5 col5 vcc vcc soe# scs1# scs0# swe# w txd0_ 6 rxdv5 rxd0_ 6 txen6 rclk5 vss vss scs3# scs2# ha0 hcs# scs4# y crs6 rxd1_ 6 txd1_ 6 tclk6 vss gnd gnd hclk hd15 intrq # ha1 ha2 aa rxd3_ 6 rxd2_ 6 txd2_ 6 rclk6 gnd vdd vcc vcc vss vss vss gnd hd1 hd0 iow# ior# ab rxdv6 col6 txd3_ 6 tclk7 vdd vcc vcc nc vcc vcc tclk9 rxd3_ 10 vss vss crs10 rclk1 1 vcc vcc vcc test12 vdd vss hd3 hd13 hd2 hd14 ac rxd1_ 7 crs7 txd1_ 7 rclk7 eec rclk8 tclk8 rxd3_ 9 rxd2_ 9 rclk9 txd2_ 9 rxd2_ 10 rclk1 0 tclk1 0 rxd3_ 11 rxdv1 1 tclk1 1 crs11 test7 test11 test16 test17 hd5 hd11 hd4 hd12 ad rxd0_ 7 txd0_ 7 rxd3_ 7 col7 eeio rxd0_ 8 txd0_ 8 txd3_ 8 rxd1_ 9 txen9 txd3_ 9 rxd1_ 10 txen1 0 txd2_ 10 rxd2_ 11 txen1 1 txd2_ 11 test3 test6 test10 test15 test20 test23 hd9 hd6 hd10 ae txen7 rxdv7 txd2_ 7 mdc rxd2_ 8 rxdv8 txd1_ 8 col8 rxd0_ 9 txd0_ 9 col9 rxd0_ 10 txd0_ 10 txd3_ 10 rxd1_ 11 txd0_ 11 txd3_ 11 test2 test5 test9 test14 test19 test22 test25 hd8 hd7 af txd3_ 7 rxd2_ 7 mdio rxd3_ 8 rxd1_ 8 txen8 txd2_ 8 crs8 rxdv9 txd1_ 9 crs9 rxdv1 0 txd1_ 10 col10 rxd0_ 11 txd1_ 11 col11 test1 test4 test8 test13 test18 test21 test24 test26 reset #
via technologies, inc. preliminary VT6516 datarsheet - 13 - l ogic s ymbol VT6516 sdram interface 64 md[63:0] 12 ma[11:0] 2 ba[1:0] 2 ras[1:0] 2 cas[1:0] 2 dwe[1:0] 4 dcs[3:0] 32 sd[31:0] 18 sa[17:0] 5 scs[4:0] sads sram interface soe swe host interface 3 ha[2:0] 16 hd[15:0] hcs ior iow intrq 12 txd0[11:0] 12 txd1[11:0] 12 txd2[11:0] 12 txd3[11:0] 12 tclk[11:0] 12 txen[11:0] 12 col[11:0] 12 crs[11:0] 12 rxd0[11:0] 12 rxd1[11:0] 12 rxd3[11:0] 12 rxd2[11:0] 12 rclk[11:0] 12 rxdv[11:0] mii interface miscellaneous interface 26 test[26:1] eec eeio mdc mdio rclk50 dclk sclk hclk reset rmii interface 16 crs_dv[15:0] 16 rxd0[15:0] 16 rxd1[15:0] 16 txen[15:0] 16 txd0[15:0] 16 txd1[15:0]
via technologies, inc. preliminary VT6516 datarsheet - 14 - p in d escriptions no. name type description sdram interface see ball table md[63:0] i/o sdram data: 64 -bit sdram data bus. these signals connect directly to the data input/output pins of the sdram devices. see ball table ma[11:0] o sdram address bus: 12 -bit sdram data bus. these signals connect directly to the address input of the sdram devices. see ball table ba[1:0] o bank identifier for bank 0 and 1: see ball table ras [1:0] o row address strobes for bank 0 and 1: dram row address strobes. ras [0] is used for bank 0. ras [1] is used for bank 1. see ball table cas [1:0] o column address strobes for bank 0 and 1: dram column address strobes. cas [0] is used for bank 0. cas [1] is used for bank 1. see ball table dwe [1:0] o dram write enable for bank 0 and 1: see ball table dcs [3:0] o dram chip select: vt-3061a supports at most 4 sdram dimm modules. sram interface see ball table sd[31:0] i/o sram data: 32 -bit sram data bus. these signals connect directly to the data input/output pins of the sram devices. see ball table sa[17:0] o sram address bus: 18 -bit sdram data bus. these signals connect directly to the address input of the sdram devices. see ball table scs [4:0] o sram chip select: sram type chip select pins address pins ---------------- ---------------------- ------------------ 32kbx32 scs[0] & sa[15] sa[14:0] 64kbx32 scs[0] & sa[16] sa[15:0] 128kbx32 scs[0] & sa[17] sa[16:0] 256kbx32 scs[0] sa[17:0] see ball table sads [1:0] o synchronous processor address status see ball table soe [1:0] o output enable see ball table swe [1:0] o sram write enable: miscellaneous interface
via technologies, inc. preliminary VT6516 datarsheet - 15 - see ball table eec o serial eeprom interface clock output: eeprom device addressing in the demo board: page 0 (eeprom): device address = 1010 000 xxxxxxxx page 1 (eeprom): device address = 1010 001 xxxxxxxx page 2 (eeprom): device address = 1010 010 xxxxxxxx page 3 (eeprom): device address = 1010 011 xxxxxxxx page 4 (sdram bank-0): device address = 1010 100 xxxxxxxx page 5 (sdram bank-1): device address = 1010 101 xxxxxxxx see ball table eeio i/o serial eeprom interface data i/o see ball table mdc o management interface (mi) clock output see ball table mdio i/o management interface (mi) data i/o see ball table rclk50 i main reference clock: see ball table dclk i sdram reference clock: see ball table sclk i sram reference clock see ball table hclk o host reference clock hclk is determined by the strapping pins in sysled[3:1], i.e. the jump selection of j1[5-6, 3-4, 1-2]: j1[off,off,off] => 8mhz j1[ off,off, on] => 16mhz j1[off, on, off] => 25mhz j1[off, on, on] => 4mhz j1[ on,off,off] => 33mhz see ball table reset i system reset see ball table sysled[26:0 ] o system output pins for led: sysled[8:0] are connected to pull-up io pads for strapping. sysled[25:9] are connected to io pads without pull up/down. all sysled[25:0] are host interface
via technologies, inc. preliminary VT6516 datarsheet - 16 - see ball table ha[2:0] i host ide-interface address bus: 3 ? b000: command the switch that the whole 16-bit data in the host data bus hd[15:0] is valid for packet-data read/write. 3 ? b001: command the switch that only the 8-bit data in the host data bus hd[15:0] is valid for internal registers read/write. 3 ? b010: command the switch to write the low byte in the host data bus hd[15:0] into the low byte of the 16-bit switch address register for internal registers reference. 3 ? b011: command the switch to write the low byte in the host data bus hd[15:0] into the high byte of the 16-bit switch address register for internal registers reference. 3 ? b1xx: bus-idle command. keep this address bus to be 3 ? b111 as the host has no access to vt-3061a. see ball table hd[15:0] i/o host ide-interface data bus: the whole 16-bit data bus is valid for packet data read/write. however, only the 8-bit data bus is valid for internal registers read/write. see ball table hcs i host chip select: active low. hcs must be asserted during the access of host ide interface. see ball table ior i io read: high-to-low edge trigger. ior must be asserted from high to low to begin the read cycle of host ide interface. see ball table iow i io read: high-to-low edge trigger. iow must be asserted from high to low to begin the write cycle of host ide interface. see ball table intrq o interrupt request: connected to the host external interrupt pin. it is asserted as the following four interrupt events happen: (1) mii management registers read/write command done (2) eeprom read/write command done (3) receiving a packet destined to host (4) finishing transmission of a packet issued by host the interrupt cause is recorded in register irqsts[3:0] in address 2000h. to clear the individual interrupt, the corresponding register has to be written: (1) register clr_phy_int in 1806h for phy interrupt. (2) register clr_ee_int in 1c04h for eeprom interrupt. (3) register clr_rcv_int in 6403h for packet-receiving interrupt. l register clr_sent_int in 6411h for packet-sent interrupt. mii interface see ball table tclk[11:0] i transmit clock for port 0-11: tclk is driven by the phy device. tclk is a continuous clock that provides the timing reference for the transfer of the txen and txd signals to the phy. a phy operating at 100mbps must provide a tclk frequency of 25mhz and a phy operating at 10mbps must provide a tclk frequency of 2.5mhz.
via technologies, inc. preliminary VT6516 datarsheet - 17 - see ball table txd<3:0>[11: 0] o transmit data for port 0-11: txd is a bundle of 4 data signals (txd<3:0>) that shall transition to the tclk. for each tclk period in which txen is asserted, txd<3:0> are accepted for transmission by the phy. txd<0> is the least significant bit. while txen is de-asserted, txd<3:0> shall have no effect upon the phy, and the value of txd<3:0> is unspecified. see ball table txen[11:0] o transmit enable for port 0-11: txen shall transition synchronous to the tclk. txen indicates the nibbles presenting on the mii for transmission. it shall be asserted synchronously with the first nibble of the preamble and shall remain asserted while all nibbles to be transmitted are presented to the mii. see ball table col[11:0] i collision detected for port 0-11: col shall be asserted by the phy asynchronously upon detection of a collision on the medium, and shall remain asserted while the collision condition persists. see ball table crs[11:0] i carrier sense for port 0-11: crs shall be asserted by the phy asynchronously upon detection of a non-idle medium or while tx_en is asserted. crs shall be de-asserted by the phy asynchronously upon detection of idle conditions on both transmit and receive media. the phy shall ensure that crs remains asserted throughout the duration of a collision condition. see ball table rxd<3:0>[11 :0] i receive data for port 0-11: rxd is a bundle of 4 data signals (rxd<3:0>) that shall transition to the rclk. for each rclk period in which rxdv is asserted, rxd<3:0> from the phy are accepted by the switch ? s mac. rxd<0> is the least significant bit. while rxdv is de-asserted, rxd<3:0> shall have no effect upon the switch ? s mac, and the value of rxd<3:0> is unspecified. see ball table rclk[11:0] i receive clock for port 0-11: rclk is sourced from the phy. rclk is a continuous clock that provides the timing reference for the transfer of the rxdv and rxd signals from the phy. a phy operating at 100mbps must provide a rclk frequency of 25mhz and a phy operating at 10mbps must provide a rclk frequency of 2.5mhz. see ball table rxdv[11:0] i receive data valid for port 0-11: rxdv is driven by the phy to indicate the nibbles presenting on the mii for receiving. rxdv shall transition synchronous to the rclk. it shall be asserted synchronously with the first nibble of the preamble and shall remain asserted while all nibbles to be received are presented to the mii. note: some flat mii input pin when the VT6516 under the rmii application, please use 22 ohm resister pull down, refer to table xxxx
via technologies, inc. preliminary VT6516 datarsheet - 18 - rmii interface see ball table crs_dv[15:0 ] i carries sense and data valid from port 15 to port 0 : see ball table rxd0[15:0] i receive data zero from port 15 to port 0 : see ball table rxd1[15:0] i receive data one from port 15 to port 0 : see ball table txen[15:0] o transmit enable from port 15 to port 0 : see ball table txd0[15:0] o transmit data zero from port 15 to port 0 : see ball table txd1[15:0] o transmit data one from port 15 to port 0 : power supply & ground see ball table vdd, vdda p positive 3.3v supply: supply power to internal digital logic, digital i/o pads, and td, tx pads. double bonding may be required. see ball table vss, vssa g negative supply: digital ground. multiple bonding pads are required to separate core and i/o pads ground. j umper s trapping jumper pin description host clock j1 [5-6], [3-4], [1- 2] sysled[3: 1] host clock (hclk) rate selection: j1[off,off,off] (sysled[3:1]==3 ? b111) => 8mhz j1[ off,off, on] (sysled[3:1]==3 ? b110) => 16mhz j1[off, on, off] (sysled[3:1]==3 ? b101) => 25mhz j1[off, on, on] (sysled[3:1]==3 ? b100) => 4mhz j1[ on,off,off] (sysled[3:1]==3 ? b011) => 33mhz phy mode j1 [7-8] sysled[4] phy device selection: j1[off] (sysled[4]==1 ? b1) => rmii phy j1[ on] (sysled[3:1]==1 ? b0) => mii phy sram type j1 [11-12,9-10] sysled[6: 5] sram device type selection: j1[off,off] (sysled[6:5]==2 ? b11) => 64k x 32 s ram j1[off,on] (sysled[6:5]==2 ? b10) => 128k x 32 sram j1[on,off] (sysled[6:5]==2 ? b01) => 32k x 32 sram
via technologies, inc. preliminary VT6516 datarsheet - 19 - s ection i f unctional d escriptions 1. g eneral d escription the VT6516 is a switch engine chip implementation of a 16 ports 10/100m ethernet switch system for ieee 802.3 and ieee 802.3u network. each of individual port can be either auto-sensing or manually selected to run at 10mbps or 100mbps speed rate and under full or half duplex mode. there are sixteen independent macs within the VT6516 chip. the mac controller controls the receiving, transmitting, and deferring of each individual port, and the mac controller also provides framing, fcs checking, error handling, status indication and flow control function. the VT6516 10/100m n-way switch port ic is wire-speed performance and low-cost packet switch; it can forward up to 148,810 packets/sec on each ethernet port. the VT6516 support 12 ports mii or 16 ports rmii (reduce mii) interface for network interface, the VT6516 used the simple 8/16 bits isa-like interface to support initiation, expansion and management. the system cpu can access various registers inside VT6516 through a simple isa-like cpu interface. the cpu can configure the switch by writing into the appropriate registers, or retrieve the status of the switch by reading the corresponding registers. the cpu can also access the register of external transceiver (phy) device through the cpu interface. the VT6516 supports new features including port based vlan , 802.3x flow control, and the VT6516 also support the sniffer function to monitor network traffic in special ports. 2. t he via e ther s witch a rchitecture the VT6516 switch engine uses the shared memory architecture. in order to improve the packet latency, VT6516 provides two methods for packet switching, one is cut-through, another is store-and-forwarding. a typical packet flow for ethernet switch is described as follows in 4.5. 2.1 switch initialization procedures 1. test all of the on board components except the switch chip or access via the switch chip, including uart, led, etc. 2. switch sdram test --- switch chip sdram control hardware initialization, configuration, sdram size determination (via embedded eeprom in sdram module) and read write test. 3. switch sram test --- switch chip sdram control hardware initialization and read write test. note that the sram size determination is via strapping. 4. switch io registers read write test. 5. ethernet phy registers read write test ---- the cpu read/write to phy devices will go through phy control in switch chip. although they are outside components, but we test them as part of the switch chip. 6. determine link table size; reset free buffer list pointers of bank 0 and 1; initialize free memory block counter. note that permanent buffer management is controlled by allocating bit mask. they will be cleared automatically in the hardware reset or software reset. 2.2 packet switching flow 1. after the switch microprocessor activates a port during initialization, the input control of that port pre- allocates one packet buffer from buffer pool. in the beginning, the buffer allocated will be from private buffer pool, but subsequent buffers may come from either private or public buffer pools.
via technologies, inc. preliminary VT6516 datarsheet - 20 - 2. when receive mac (rmac) receives a packet data from the network interface ? either through mii or reduced mii (rmii) ? it packs the data into 16-bit word then passes it to input control. if rmac detects any error, it also notifies input control to stop forwarding process. 3. input control extracts the destination mac address from incoming data, passes it along to forwarding table control for forwarding decision. in the mean while, it packs 16-bit words into 64-bit quad-words, and saves it to an input fifo before storing the packet data to sdram. 4. if the switch is configured to ? store and forward ? mode, input control queues the packet to the output queue of the destination port after input control is informed by rmac that this is a good packet and it stores all packet data to sdram. if the switch is configured to ? cut-through ? mode, the input control queues the packet to the output queue of the destination port after enough amount of packet is stored in sdram to prevent output fifo under-run. 5. after the whole packet is received and fcs is correct, input control pass the source mac address of the packet to forwarding table control for address learning. 6. output control of the outbound port de-queue the packet from output queue, and fetch packet data from sdram and save it into output fifo. then it notifies the transmit mac (tmac) of the new packet to transmit. 7. tmac grabs 16-bit at a time from output control, adds preamble and sfd to the beginning of the packet, then send them out. proper deferring is done if necessary to conform to 802.3 standard. 8. after the packet is successfully transmitted, tmac notifies output control of the successful transmission. output control then returns the packet to buffer pool. 3. i nterface d escriptions b uffer m emory (sdram) i nterface and t able (ssram) i nterface VT6516 provides a 64-bit sdram/sgram interface for packet buffering and a 32-bit synchronous sram (ssram) interface for maintaining address table and various link lists. VT6516 uses sdram as packet buffers. each packet buffer is a 1536-byte contiguous memory block in sdram, and corresponds to a 12-byte link node data structure in ssram. except the first 128 link nodes, each link node can be part of an output queue, a free buffer link list, or held in input or output control. the first 128 link nodes are divided into 16 groups, each pre-assigned to a specific input control, and bit-mapped inside buffer control for faster allocate/free operation and reduce ssram usage. initially, each input port control would request one packet buffer from its private buffer pool. each time when a packet buffer is consumed by an incoming packet, the input port control will request another packet buffer to prepare for next packet. the common shared packet memory will be allocated only when there ? s no free permanent packet memory for that port. see figure 3-4.
via technologies, inc. preliminary VT6516 datarsheet - 21 - address table entriers permanent buffer table free list link table 12 bytes/entry 12 bytes/entry 128 entries 1.5 k/packet 1.5 k/packet ... 128 blocks sram dram
via technologies, inc. preliminary VT6516 datarsheet - 22 - figure 3- 3 following as the listing and figure 3-6 is the algorithm of initialization procedures for 2 bank free list of sdram. for 16 mbit sdram as following, -- bank0 free link list: 128, 129, 131, 134, 136, 137, 139, 142, 144, 145, 147, 150, 152, 153, 155, 158, 160,... -- bank1 free link list: 130, 132, 133, 135, 138, 140, 141, 143, 146, 148, 149, 151, 154, 156, 157, 159, 162, 164, ... for 64 mbit sdram as following, -- bank0 free link list: 128 , 129 , 130 , 134 , 135 , 139 , 140 , 141 , 144 , 145 , 146 , 150 , 151 , 155 , 156 , 157 , 160 , ... --bank1 free link list: 131 , 132 , 133 , 136 , 137 , 138 , 142 , 143 , 147 , 148 , 149 , 152 , 153 , 154 , 158 , 159 , 163 , ? figure 3-6: algorithm of initialization of free link lists. #define sram_addr_reg0 0x2001 #define sram_addr_reg1 0x2002 #define sram_addr_reg2 0x2003 #define sram_data_reg0 0x2004 #define sram_data_reg1 0x2005 #define sram_data_reg2 0x2006 #define sram_data_reg3 0x2007 #define sram_cmd_reg 0x2008 #define sram_status_reg 0x2009 #define sram_access_idle 0x01 #define null_ptr 0x7ffff void writelinkentry(int entryid, int nextid) { reg_byte_ write ( sram_addr_reg0, entryid*3 & 0x0ff ) ; reg_ byte_cont_write ( ((entryid*3) >> 8) & 0x0ff ) ; reg_ byte_cont_write ( ((entryid*3) >> 16) & 0x0ff ) ; 2k 2k 2k 2k 128/0 129/0 130/1 131/0 132/1 bank 0 bank 1 2k 133/1 2k 2k 134/0 135/1 136/0 link/ frame memory bank list 0 list 1 4k 4k 128/0 129/0 131/1 130/0 132/1 bank 0 bank 1 133/1 134/0 136/1 135/0 links/ list memory bank list 0 list 1 4k 4k 137/1 16mbits sdram 64mbits sdram
via technologies, inc. preliminary VT6516 datarsheet - 23 - reg_ byte_cont_write ( nextid & 0x0ff ) ; // data bits [7:0] reg_ byte_cont_write ( (nextid >> 8) & 0x0ff ) ; // data bits [15:8] reg_ byte_cont_write ( (nextid >> 16) & 0x0ff ) ; // data bits [23:16] reg_ byte_cont_write ( 0 ) ; // data bits [31:24] reg_ byte_cont_write ( 0x02 ) ; // sram-write command while ( reg_ byte _ read ( sram_status_reg ) != sram_access_idle) {} } void initfreelist16mb(int maxlinkentryno) { // note: for 16mb sdram, // bank0 free list head pointer = 128 // bank1 free list head pointer = 130 int k; // k: current free entry id int b0, b1; // b0, b1: bank0/1 free list head entry id for(b0=b1= null_ptr, k= maxlinkentryno; k <=128; k--) if (((k * 3) % 8) < 4) { writelinkentry(b0,k); b0=k;} else { writelinkentry(b1,k); b1=k;} } void initfreelist64mb(int maxlinkentryno) { // note: for 64mb sdram, // bank0 free list head pointer = 128 // bank1 free list head pointer = 131 int k; // k: current free entry id int b0, b1; // b0, b1: bank0/1 free list head entry id for(b0=b1= null_ptr, k= maxlinkentryno; k <=128; k--) if (((k * 3) % 16) < 8) { writelinkentry(b0,k); b0=k;} else { writelinkentry(b1,k); b1=k;} }
via technologies, inc. preliminary VT6516 datarsheet - 24 - 3.1.1 sdram interface all frames received by the VT6516 will be stored into a common frame buffer memory, sdram.the sdram contains the packet buffers, each buffer is a 1536 (1.5k) bytes memory block. each block is associated to an entry in link table in sram. the link entry includes a field (19 bits to support 512 mb) to point to next link entry. the figure 3-2 is buffer link list structure. in order to provide the cost effective dram buffers, user can connect the 32 bits data sgram with VT6516 switch, there are two external buffer device using two double bank 128kbits by 32 required. the following figure shows the minimum configuration of buffer memory and link/address memory. note that the sgram physical memory hole is to accommodate the forwarding table into the sram link list hole. VT6516 32*32 (128kb) ssram by one 128k*32*2 (2mb) sgram by two memory hole (14mb) physical device (1mb) physical device (1mb) physical buffer memory allocation (eg, 2mb) address table entries (link-list hole) link list link list physical sram memory allocation (eg, 128k)
via technologies, inc. preliminary VT6516 datarsheet - 25 - the detail initial step of VT6516 as following, 1. forwarding table base = 683 * 3 2. sdram type equal to 16m bit 3. end0-3 = 2 (16mb) 4. free list of sram have to be constructed by release public node in the sequence of buffers with blocks number 10922, 10911, ? . 10240, 681, 680, 128 note: the buffers numbered 682 to 10239 are located in the buffer memory hole, those buffers will be not put into the free list. 5. free memory count equal to 1364 otherwise like this minimum configuration, the entries support for difference sram size using normal address table followed by free-list, the following table show the address entries support buffers 32*32 ssram 64*32 64*64 2mb 8k entries 8k~16k 8k~64k 4mb 8k entries 8k~16k 8k~64k
via technologies, inc. preliminary VT6516 datarsheet - 26 - 3.1.2 sram interface the feature 3-1 is ssram structure map, the ssram contains the forwarding address entries, sdram buffers link list and permanent buffers table. figure 3-1 sram address table entries permanent link table link table address entries * 12 bytes/entry (2 hash_bits(1400h) * 12) forwarding table start address (table_base(1401h) ) low high 0 link table entries * 12 bytes/entry (freecnt(1006h) * 1.5k) 16 ports * 8 * 12 bytes/entry
via technologies, inc. preliminary VT6516 datarsheet - 27 - figure 3-2 free buffer link structure table 1-0 free buffer link structure bit 18-0 next entry pointer bit 35-19 port mask (bit[16]: cpu port + bit[15:0]: ethernet ports 0~15) bit 46-36 packet byte count bit 50-47 source port id bit 51 frame type reserved (zero) bit 54-52 priority bit 57-55 frame tag type reserved (zero) bit 58 vlan tag flag reserved (zero) bit 64-59 vlan id bit 95-65 reserved for future figure 3-5 the address table entries structure + the address table structure as figure 3-5, the address table entries contains the mac address information from bit 11 to bit 47, others bits 0~10 or bits 0~14 (2k~32k) as the address entries hashing index, the total address entries of device assigned by the hash_bits (1400h). initialization procedures include to set forwarding address table control in normal mode and to invalidate all forwarding table entries by setting the age-count field as 0. configure port mask register (user_pm) for broadcast mac address. configure port mask and mac address pairs that allow any static mac to port mask mapping. forwarding table entry has 96 bits, defined as follows: priority 54 frame type 52 51 source port id 50 47 packet byte count 46 36 port mask 35 19 pointer to next entry 18 0 frame tag type 57 55 16 ports +1 cpu reserved vlan tage flag 58 vlan id 64 59 65 95 56 static/dynamic flag age count 55 54 port mask 53 37 36 0 63 58 16 ports +1 cpu reserved vlan tage flag 57 vlan id 64 95 bit-47:11 mac address fixed, even for key length = 11~15
via technologies, inc. preliminary VT6516 datarsheet - 28 - table 1-1 address table structure bit 36-0 high bits (bit 47-11) of mac address bit 53-37 port mask (bit[16]: cpu port + bit[15:0]: ethernet ports 0~15) bit 55-54 age count bit 56 static flag (0: dynamic entry, 1: static entry that can not be updated) bit 57 vlan tag flag reserved (zero) bit 63-58 vlan id bit 95-64 reserved for future and following is the algorithm for the initial the address entries; #define sram_addr_reg0 0x2001 #define sram_addr_reg1 0x2002 #define sram_addr_reg2 0x2003 #define sram_data_reg0 0x2004 #define sram_data_reg1 0x2005 #define sram_data_reg2 0x2006 #define sram_data_reg3 0x2007 #define sram_cmd_reg 0x2008 #define sram_status_reg 0x2009 #define sram_access_idle 0x01 void invalidateforwardentry(int entryid) { // the entryid is starting from maxlinkentryid with width of 96 bits reg_byte_ write ( sram_addr_reg0, (entryid*3+1) & 0x0ff ) ; reg_ byte_cont_write ( ((entryid*3+1) >> 8) & 0x0ff ) ; reg_ byte_cont_write ( ((entryid*3+1) >> 16) & 0x0ff ) ; reg_ byte_cont_write ( nextid & 0x0ff ) ; entry bits [32] reg_ byte_cont_write ( (nextid >> 8) & 0x0ff ) ; reg_ byte_cont_write ( (nextid >> 16) & 0x0ff ) ; reg_ byte_cont_write ( (nextid >> 16) & 0x0ff ) ; reg_ byte_cont_write ( 0x02 ) ; // sram-write command while ( reg_ byte _ read ( sram_status_reg ) != sram_access_idle) {} } 3.1.3 cpu interface the VT6516 support one isa-like cpu interface, this cpu interface can cooperate wi th one simple microprocessor like 8031 or 8051. the cpu will access the switch control and status register to perform initialization and configurations. by the cpu interface, the frames of cpu port can be read/written from/into the buffer. the cpu interface can also be used to access the internal registers. the cpu interface also used to access the external phy devices through the phy control module. the cpu firmware will perform following tasks, - read the configuration from switch register or from the eeprom contains - initialize the switch followed by the configuration, those task including * dram initialization * sram initialization and link list construction * program for each network ports for users manual setting or read the auto-negotiation result - start switch to receive frames and forward frames - decrease the learning address aging count - polling the network port change event and change the switch mac negotiation mode.
via technologies, inc. preliminary VT6516 datarsheet - 29 - - receiving the stp defined bpdu packets - blocking or re-start port due to stp - access the network management counter of each port for a management switch the cpu also perform the management function like receiving and transmitting the snmp frame.
via technologies, inc. preliminary VT6516 datarsheet - 30 - 3.1.4 network interface the VT6516 directly connect to 16 port rmii phy or 12 port mi i phy device which compliant with ieee standard (please see ieee 802.3u fast ethernet standard) . each fast ethernet port has following characteristics: - capable of supporting both 10mbps and 100mbps data rates in half and full duplex modes. - provide a simple management interface (smi) for port status - perform all functions of the ieee 802.3 protocol such as frame formatting, frame stripping, collision handling, deferred, etc. - adjustable preamble ,sfd and inter frame gap (ifg). - ieee 802.3x flow control supported - ieee 802.1d spanning tree protocol support, and all port state of listen and block configurable 3.1.4.1 rmii interface the VT6516 communicates with the external 10/100m ethernet transceiver through the reduced mii (rmii) interface. the signals of rmii interface are described in table-3-1 table 3-1 rmii interface signals name type description crsdv i carrier sense and data valid rxd[0-1] i receive data bit 0 to 1 , data rate with 50mhz txen o transmit enable txd[0-1] o transmit data bit 0 to 1 figure 3-1 rmii timing diagram (omitted)
via technologies, inc. preliminary VT6516 datarsheet - 31 - 3.1.4.2 mii interface the VT6516 communicates with the external 10/100m ethernet transceiver through standard mii interface, in this mode the VT6516 became 12 ports mii port due to the mii signal multiplexed with rmii signal. but the ports number of internal remained as 16 ports. the signals of mii interface are described in table-3-2: table 3-2 mii interface signals name type description tclk i transmit clock txd[3:0] o transmit data for . txen o transmit col i collision detected crs i carrier sense rxd[3:0] i receive data rclk i receive clock rxdv i receive data figure 3-2 mii timing diagram (omitted) 3.1.4.3 flow control under full-duplex mode operation, if the buffer utilization of whole switch has exceeded the upper threshold and the permanent buffer has been used up, a pause frame with a pause time interval will be send to the sending port to stop it from sending new frame. if register- fmfct not enable at this switch, the public buffer will used until no more buffers. then further incoming frames will be dropped. the unit in pause time field of the flow control frame is slot time (512 bits). the max possible waiting time should be the max packet memory size divided by lowest port speed, for example if 512mb is the max packet buffer size and 10mb is the lowest speed, the 512m * 8 bits * 100ns = 409.6 seconds (8m slot time) is the max possible waiting time. the congestion factor is the max possible waiting time at current link load. the pause timer value is half of the max possible waiting time. if it is greater than the feasible max pause time, use all 1 ? s in pause time value. if the utilization of the public buffer of the switch drops below the lower threshold, a pause-frame with minimum frame interval of 0 will be sent to the linking ports the enable new frame transmission. under half duplex operation, if the buffer utilization of whole switch has exceeded the upper threshold and the permanent buffer has been used up, the port will perform back-pressure based flow control by sending a jam pattern on each incoming frame. if backpressure flow control of the port is not enable, the frame will be dropped. the flow control pause time is calculated by maintained the configuration of port speed of each port and the buffer size. with input of the free memory block count and congestion factor, it determines flow control on or off on an output port. if flow control is on, any new queue request from a input port to this output port will trigger a flow control frame sent to that request port by the output mac that is notified by the packet flow control unit.
via technologies, inc. preliminary VT6516 datarsheet - 32 - the flow control activity is triggered when the buffer utilization exceeds certain thresholds specified by the dedicated register fmfct, register- fmfct is used to specify the upper and lower thresholds of reserved buffer slot for whole switch. 3.1.4.4 smi interface the VT6516 communicates with the external 10/100m phy and access the phy register through mdc, mdio 3.1.4.5 auto negotiation the VT6516 communicates with the external 10/100m phy and access the phy register through mdc, mdio 3.1.5 serial eeprom interface
via technologies, inc. preliminary VT6516 datarsheet - 33 - 4. f unctional d escription 4.1 packet reception and address recognition when VT6516 received frames from network, the input control module will receive packet from input mac module, then get the output port mask from forwarding table control module, request packet buffer from buffer control, write packet from input fifo to packet buffer scheduled by scheduler module, queue packet to the output queue through queue control module. and update the forwarding table by the source address of the received good packet. usually the source mac address will be learned and stored to forwarding table. if vlan is configured by user, the frame tag type and vlan id will also be learned. the source mac address bit 47~11 and vlan id will be record in the forwarding table entry indexed by source mac address bit 10~0 or 14~0. the on chip multicast forwarding configuration registers mainly are for well-known addresses which are listened by cpu. external multicast addresses are for dynamically assigned. also some static mac addresses/port mask registers can be configured by cpu, these addresses will also be checked before look up the forward table. 4.2 packet forwarding and vlan the VT6516 ? s queue control maintains all head and tail pointers for all output ports. accept the request to queue and dequeue packets from input and output control. both queue and dequeue operations take only 1 sram access (3 words = 96 bits), because the tail node is stored in the internal register of the queue control usually, queue and dequeue operations to a specific output queue can be performed simultaneously. however, mutual exclusion is applied while only one node in this queue each port will maintain a packet counter, it increments when packet gets queued through the tail pointer, it decrements when packet de-queued through head pointer. the congestion factor is the queued packet count divided by port media speed. the congestion factor will be used for flow control and multicast, congestion factor should be roughly equal to the time it takes to transmit all the queued packets. for multicast packet, based on congestion factor, the least congested output port will be queued first. the output control will queue the packet to next least congested output port when it is transmitted, the cpu port will always be last port to be transmitted if the corresponding cpu bit is set in the port mask. the port speed will be used for cut through forwarding decision. if the packet length is 7ff, it implies the input control try to cut through, queue control will accept or reject by looking whether the input port speed is equal to the output port speed and the output don ? t have queued packets and any pending transmission. the faster output port (than input port speed) and cpu port is not able to cut through broadcast packet, multicast and look up miss packet will forward(multicast) to those ports which is configured by software, but default(dump switching hub) will be all ports(or all ports in that vlan if vlan is implemented) except cpu port. broadcast, multicast packet will check the on chip broadcast forwarding configuration register and multicast forwarding configuration registers first, if multicast address not match any of the multicast forwarding configuration registers then it will look up the external sram forwarding table.
via technologies, inc. preliminary VT6516 datarsheet - 34 - when request transfer to or from sdram through scheduler, the input control need to derive each burst starting address to bank0 or bank1 information for scheduler to utilize sdram bandwidth efficiently. when input fifo is filled to 12x64 or page boundary or end of frame, the input port control will request dram access to write packet. input fifo size is 64 bits by 24. after receiving the grant of queueing (cut-through or store-and-forward), even the bad packet has to be forwarded. while cut-through, the input control will request the grant of cut-through counter bus for passing the cut through packet count from input port to output port as the whole packet has received. 4.2.1 cross vlan server port support the VT6516 support cross vlan server port configuration, the following illation show the sample of server ports configuration by set the register of server port mask(14a0h~14a1h), and server ports only enable after the vlan enabled. the multicast or broadcast frames received from one vlan group will forward to any server ports and only forward to the ports with same vid. 4.3 network management features flow control the flow control activity is triggered when the buffer utilization exceeds certain thresholds specified by the dedicated register xxxx, register-xxxx is used to specify the upper and lower thresholds of reserved buffer slot for whole switch. under full-duplex mode operation, if the buffer utilization of whole switch has exceeded the upper threshold and the permanent buffer has been used up, a flow control with a predefined pause time value will be sent to the source port to stop the input traffic. if flow control mechanism is not enabled, the public buffer will exhausted so that the further incoming frames will be dropped. under half duplex operation, if the buffer utilization of whole switch has exceeded the upper threshold and the permanent buffer has been used up, the port will perform back-pressure based flow control by sending a jam pattern on each incoming frame. if backpressure flow control of the port is not enable, the frame will be dropped. sniffer port the VT6516 support sniffer function for user to monitor the network traffic. the sniffer port enable can be set for any individual port of sixteen ports. and each sniffer port can set to monitor the traffic coming from any others fifteen port(monitor port). any packets sent to the monitor ports or transmitted out of monitor port will be forwarded to sniffer port. spanning tree support the VT6516 support the spanning tree protocol (stp). when spanning tree protocol support is enabled, frames from the cpu port having a da value equal to reserved bridge management group address for bpdu will be forwarded to the port specified by the cpu. frames from other port with a da equal to reserved bridge management group address for bpdu will be forwarded to the cpu port.
via technologies, inc. preliminary VT6516 datarsheet - 35 - every port of the VT6516 can be set to block and listen mode through the cpu interface. in the mode, incoming frames with da value equal to the reserved group address for bpdu will be forward to cpu port and other incoming frames with other da value will be dropped. outgoing frames with any da value will be filtered expect da equal to bpdu.
via technologies, inc. preliminary VT6516 datarsheet - 36 - s ection ii r egister m ap 1. r egister t ables the VT6516 incorporates the required command/status registers and various counters for management purposes. although the default values of the control registers are predefined in the usual way, there is still a requirement for cpu intervention. all registers are defined as 8 bits so that long registers have to be divided into pieces of 8 bits with the little-endian principle, i.e. the lower byte in the lower address. there are only eight registers that are directly accessible for cpu, called the cpu interface registers. they are located with memory mapping in the range of 8000h ~ 8007h for the microprocessor 8031 in the evaluation board. the other registers are called the internal registers that are referenced indirectly by the 16-bit address register with offset 02h ~ 03h in the cpu interface address table. while the 16-bit address register is set to reference to the specific 8-bit internal register, the following read or write operation to the 8-bit data register with offset 01h in the cpu interface address table will cause the specified internal register to be read or written indirectly. besides, the address register will increase by one automatically to facilitate the successive read/write operation. if the internal register is of size less than 8 bits, the value 0 ? s is always returned for the vacant register space and any write operations to them take no effect. 2 cpu i nterface r egisters m ap *note: register table base = 8000h for the evaluation board. description type offset function packet data register [15:0] r/w 0h according to the strapping mode of packet read/write data bus, two types are defined for 8- bit and 16-bit data bus, respectively. for 8-bit cpu, only the low byte of the packet data register is used for packet read/write. for 16-bit cpu, the whole 16-bit packet data register is used for packet read/write. data register [7:0] r/w 1h the read or write operation to the 8-bit data register will cause the specified internal register (referenced by the address register) to be read or written indirectly. besides, after the read/write operation, the address register will increase by one automatically to facilitate the successive read/write operation. address register [7:0] r/w 2h the low-byte address register for the reference to an internal register with 16-bit address. address register [15:8] r/w 3h the high-byte address register for the reference to an internal register. test register 0 [7:0] w/o 4h see the description in test register 3 test register 1 [7:0] w/o 5h see the description in test register 3 test register 2 [7:0] w/o 6h see the description in test register 3 test register 3 [7:0] w/o 7h
via technologies, inc. preliminary VT6516 datarsheet - 37 - 3 s witch i nternal r egisters m ap address (base/offse t) register description name bits default value r/ w 0000h sdram 00h sdram type sdramtype [0] 0 r/ w 01h cas latency cl [1:0] 2 r/ w 02h sdram operation mode rsdm [3:0] 5 r/ w 03h dim-bank 0 ending address end0a [4:0] 0 r/ w 04h dim-bank 1 ending address end1a [4:0] 0 r/ w 05h dim-bank 2 ending address end2a [4:0] 0 r/ w 06h dim-bank 3 ending address end3a [4:0] 0 r/ w 07h sdram command drive strength configure sdram_dr_c fg [2:0] 0 r/ w 08h sdram bank interleaving disable bk_il_dis [0] 0 r/ w 0800h sram 00h sram read command interleave disable sram_read_il_d is [0] 0 r/ w 0c00h queue control 00-02h free memory flow control threshold register fmfct [18:0 ] 0 r/ w 03h cut through enable cut_throu gh_en [0] 0 r/ w 04h cpu port speed configuration cpu_spd_cf g [2:0] 0 r/ w 10-13h congestion factor of output port 0 congest_fc t0 [25:0 ] 0 r/o 14-17h congestion factor of output port 1 congest_fc t1 [25:0 ] 0 r/o 18-1bh congestion factor of output port 2 congest_fc t2 [25:0 ] 0 r/o 1c-1fh congestion factor of output port 3 congest_fc t3 [25:0 ] 0 r/o 20-23h congestion factor of output port 4 congest_fc t4 [25:0 ] 0 r/o
via technologies, inc. preliminary VT6516 datarsheet - 38 - 24-27h congestion factor of output port 5 congest_fc t5 [25:0 ] 0 r/o 28-2bh congestion factor of output port 6 congest_fc t6 [25:0 ] 0 r/o 2c-2fh congestion factor of output port 7 congest_fc t7 [25:0 ] 0 r/o 30-33h congestion factor of output port 8 congest_fc t8 [25:0 ] 0 r/o 34-37h congestion factor of output port 9 congest_fc t9 [25:0 ] 0 r/o 38-3bh congestion factor of output port 10 congest_fc t10 [25:0 ] 0 r/o 3c-3fh congestion factor of output port 11 congest_fc t11 [25:0 ] 0 r/o 40-43h congestion factor of output port 12 congest_fc t12 [25:0 ] 0 r/o 44-47h congestion factor of output port 13 congest_fc t13 [25:0 ] 0 r/o 48-4bh congestion factor of output port 14 congest_fc t14 [25:0 ] 0 r/o 4c-4fh congestion factor of output port 15 congest_fc t15 [25:0 ] 0 r/o 50-53h congestion factor of output port 16 (cpu port) congest_fc t16 [25:0 ] 0 r/o 1000h buffer control 00-02h bank 0 free pointer free0_pt [18:0 ] r/o 03-05h bank 1 free pointer free1_pt [18:0 ] r/o 06-08h free memory block count freemcnt [18:0 ] r/ w 09h clear all free pointers (reset the free buffer pointers according to the sdram type) cfp [0] w/ o 10h private memory allocation bit mask for port 0 port0_mask [7:0] 0 r/o 11h private memory allocation bit mask for port 1 port1_mask [7:0] 0 r/o 12h private memory allocation bit mask for port 2 port2_mask [7:0] 0 r/o 13h private memory allocation bit mask for port 3 port3_mask [7:0] 0 r/o 14h private memory allocation bit mask for port 4 port4_mask [7:0] 0 r/o 15h private memory allocation bit mask for port 5 port5_mask [7:0] 0 r/o 16h private memory allocation bit mask for port 6 port6_mask [7:0] 0 r/o 17h private memory allocation bit mask for port 7 port7_mask [7:0] 0 r/o
via technologies, inc. preliminary VT6516 datarsheet - 39 - 18h private memory allocation bit mask for port 8 port8_mask [7:0] 0 r/o 19h private memory allocation bit mask for port 9 port9_mask [7:0] 0 r/o 1ah private memory allocation bit mask for port 10 port10_mas k [7:0] 0 r/o 1bh private memory allocation bit mask for port 11 port11_mas k [7:0] 0 r/o 1ch private memory allocation bit mask for port 12 port12_mas k [7:0] 0 r/o 1dh private memory allocation bit mask for port 13 port13_mas k [7:0] 0 r/o 1eh private memory allocation bit mask for port 14 port14_mas k [7:0] 0 r/o 1fh private memory allocation bit mask for port 15 port15_mas k [7:0] 0 r/o 1400h forwarding table control 00h bits of mac address used as index for forwarding table hash_bits [2:0] 0 r/ w 01-03h starting sram address register for forwarding table base tbl_base [18:0 ] 0 r/ w 04h user configured forwarding mode fwd_mode [1:0] 0 r/ w 05-07h user configured port mask user_pm [16:0 ] 0 r/ w 08-09h port mask for packets sent by cpu cpu_pm [15:0 ] 0 r/ w 0ah cpu port related forwarding configuration. cpu_fwd_cf g [2:0] 0 r/ w 0bh port id of s niffer port. sniffer_pid [3:0] 0 r/ w 0c-0eh monitor port mask monitor_pm [16:0 ] 0 r/ w 10h high byte [14:8] of the mac hash address to be aged age_mac [6:0] 0 r/ w 11h low byte [7:0] of the mac hash address to be aged. age_mac [7:0] 0 r/ w 12h aging status aging_stat us [0] 0 r/o 20h spanning tree state for port 0 port0_stp_s tate [1:0] 0 r/ w 21h spanning tree state for port 1 port1_stp_s tate [1:0] 0 r/ w 22h spanning tree state for port 2 port2_stp_s tate [1:0] 0 r/ w 23h spanning tree state for port 3 port3_stp_s tate [1:0] 0 r/ w
via technologies, inc. preliminary VT6516 datarsheet - 40 - 24h spanning tree state for port 4 port4_stp_s tate [1:0] 0 r/ w 25h spanning tree state for port 5 port5_stp_s tate [1:0] 0 r/ w 26h spanning tree state for port 6 port6_stp_s tate [1:0] 0 r/ w 27h spanning tree state for port 7 port7_stp_s tate [1:0] 0 r/ w 28h spanning tree state for port 8 port8_stp_s tate [1:0] 0 r/ w 29h spanning tree state for port 9 port9_stp_s tate [1:0] 0 r/ w 2ah spanning tree state for port 10 port10_stp_ state [1:0] 0 r/ w 2bh spanning tree state for port 11 port11_stp_ state [1:0] 0 r/ w 2ch spanning tree state for port 12 port12_stp_ state [1:0] 0 r/ w 2dh spanning tree state for port 13 port13_stp_ state [1:0] 0 r/ w 2eh spanning tree state for port 14 port14_stp_ state [1:0] 0 r/ w 2fh spanning tree state for port 15 port15_stp_ state [1:0] 0 r/ w 80h port 0 vlan id port0_vid [5:0] 0 r/ w 82h port 1 vlan id port1_vid [5:0] 0 r/ w 84h port 2 vlan id port2_vid [5:0] 0 r/ w 86h port 3 vlan id port3_vid [5:0] 0 r/ w 88h port 4 vlan id port4_vid [5:0] 0 r/ w 8ah port 5 vlan id port5_vid [5:0] 0 r/ w 8ch port 6 vlan id port6_vid [5:0] 0 r/ w 8eh port 7 vlan id port7_vid [5:0] 0 r/ w 90h port 8 vlan id port8_vid [5:0] 0 r/ w 92h port 9 vlan id port9_vid [5:0] 0 r/ w 94h port 10 vlan id port10_vid [5:0] 0 r/ w
via technologies, inc. preliminary VT6516 datarsheet - 41 - 96h port 11 vlan id port11_vid [5:0] 0 r/ w 98h port 12 vlan id port12_vid [5:0] 0 r/ w 9ah port 13 vlan id port13_vid [5:0] 0 r/ w 9ch port 14 vlan id port14_vid [5:0] 0 r/ w 9eh port 15 vlan id port15_vid [5:0] 0 r/ w a0-a1h server port mask srv_pm [15:0 ] 0 r/ w a2h vlan related forwarding configuration vlan_fwd_c fg [0] 0 r/ w 1800h phy control 00h phy id phyid [3:0] 0 w/ o 01h phy register address phy_reg_ad dr [4:0] 0 w/ o 02-03h phy data register phydata [15:0 ] r/ w 04h phy command register phycmd [0] w/ o 05h phy status register physts [1:0] 0 r/o 10h port0 phy device address port0_phy_ addr [4:0] 0 r/ w 11h port1 phy device address port1_phy_ addr [4:0] 0 r/ w 12h port2 phy device address port2_phy_ addr [4:0] 0 r/ w 13h port3 phy device address port3_phy_ addr [4:0] 0 r/ w 14h port4 phy device address port4_phy_ addr [4:0] 0 r/ w 15h port5 phy device address port5_phy_ addr [4:0] 0 r/ w 16h port6 phy device address port6_phy_ addr [4:0] 0 r/ w 17h port7 phy device address port7_phy_ addr [4:0] 0 r/ w 18h port8 phy device address port8_phy_ addr [4:0] 0 r/ w 19h port9 phy device address port9_phy_ addr [4:0] 0 r/ w 1ah port10 phy device address port10_phy_ addr [4:0] 0 r/ w
via technologies, inc. preliminary VT6516 datarsheet - 42 - 1bh port11 phy device address port11_phy_ addr [4:0] 0 r/ w 1ch port12 phy device address port12_phy_ addr [4:0] 0 r/ w 1dh port13 phy device address port13_phy_ addr [4:0] 0 r/ w 1eh port14 phy device address port14_phy_ addr [4:0] 0 r/ w 1fh port15 phy device address port15_phy_ addr [4:0] 0 r/ w 1c00h eeprom control 00h eeprom word address eewdaddr [7:0] w/ o 01h eeprom data eedata [7:0] r/ w 02h eeprom device address eedevaddr [7:0] w/ o 03h eeprom status register eests [2:0] r/o 2000h cpu interface 00h interrupt status register irqsts [3:0] 0 r/ w 01h-03h sram address register sramaddr [18:0 ] r/ w 04h-07h sram data register sramdata [31:0 ] r/ w 08h sram command register sramcmd [1:0] r/ w 09h sram status register sramsts [1:0] 0 r/o 10h-13h sdram address register sdramaddr [23:0 ] r/ w 14h-1bh sdram data register sdramdata [63:0 ] r/ w 1ch sdram command register sdramcmd [1:0] r/ w 1dh sdram status register sdramsts [1:0] 0 r/o 20h write packet command wr_pkt_cm d [2:0] w/ o 21h packet abort err_abort [0] w/ o 30h bits [47:40] of switch base mac address [47:0] switch_ma c_base [7:0] 0 r/ w 31h bits [39:32] of switch base mac address [47:0] switch_ma c_base [7:0] 0 r/ w 32h bits [31:24] of switch base mac address [47:0] switch_ma c_base [7:0] 0 r/ w
via technologies, inc. preliminary VT6516 datarsheet - 43 - 33h bits [23:16] of switch base mac address [47:0] switch_ma c_base [7:0] 0 r/ w 34h bits [15:8] of switch base mac address [47:0] switch_ma c_base [7:0] 0 r/ w 35h bits [7:4] of switch base mac address [47:0] switch_ma c_base [7:4] 0 r/ w 40h interrupt mask register irqsts_mas k [3:0] 4 ? b1111 r/ w 50h cpu soft reset for the whole switch chip reset cpu_soft_r eset [0] 1 r/ w 51h revision control register revision_ct l [7:0] 0 r/o 2400h mac & i/o control module of port 0 00h configurable preamble bytes pream_cfg [2:0] 7 r/ w 01h configurable frame gap in di bits for 1st interval ifg_cfg [5:0] 32 r/ w 02h backoff configuration boffcfg [4:0] 5 ? b100 00 r/ w 03h mac media type configuration maccfg [3:0] 0 r/ w 04h io port enable io_cfg [1:0] 0 r/ w 10h-13h received good packet count rcv_good_p kt [31:0 ] 0 r/o 14h-17h received bad packet count rcv_bad_pk t [31:0 ] 0 r/o 18h-1bh drop packet counter drop_pkt [31:0 ] 0 r/o 1ch-1fh sent good packet count xmt_good_ pkt [31:0 ] 0 r/o 20h-23h sent bad packet counter xmt_bad_pk t [31:0 ] 0 r/o 2800h mac & i/o control module of port 1 as same as port 0 2c00h mac & i/o control module of port 2 as same as port 0 3000h mac & i/o control module of port 3 as same as port 0 3400h mac & i/o control module of port 4 as same as port 0 3800h mac & i/o control module of port 5 as same as port 0 3c00h mac & i/o control module of port 6 as same as port 0 4000h mac & i/o control module of port 7 as same as port 0 4400h mac & i/o control module of port 8 as same as port 0 4800h mac & i/o control module of port 9 as same as port 0 4c00h mac & i/o control module of port 10 as same as port 0
via technologies, inc. preliminary VT6516 datarsheet - 44 - 5000h mac & i/o control module of port 11 as same as port 0 5400h mac & i/o control module of port 12 as same as port 0 5800h mac & i/o control module of port 13 as same as port 0 5c00h mac & i/o control module of port 14 as same as port 0 6000h mac & i/o control module of port 15 as same as port 0 6400h cpu io control module 00h cpu packet read byte count register bits [7:0] pkt_byte_c nt [7:0] 0 r/o 01h cpu packet read byte count register bits [10:8] pkt_byte_c nt [10:8 ] 0 r/o 02h cpu packet read status register rd_pkt_sta tus [1:0] 0 r/o 03h packet source port id pkt_src_po rt [3:0] 0 r/o 04h cpu io port configuration register cpuio_cfg [1:0] 0 r/ w 10h cpu packet write status register wr_pkt_sta tus [2:0] 0 r/o 4. d etail of s witch r egister 4.1 registers of sdram control module * base address: 0000h addres s (offset ) function register name bits defau lt value r/ w 00h sdram type: 0: 16mbit sdram chip (default) 1: 64mbit this register has to be specified before initialization of the buffer control because the bank 1 free buffer pointer should have initial value 130 for 16mbit sdram, or, initial value 131 for 64mbit sdram. sdramtype [0] 0 r/w 01h cas latency for read operation : 2 ? b 00: latency 1 2 ? b 01: latency 2 2 ? b 10: latency 3 (default) this latency specifies the required delay between the cas cycle and the first read cycle. note that the cas latency has to be specified before using rsdm in sdram initialization. cl [1:0] 2 r/w
via technologies, inc. preliminary VT6516 datarsheet - 45 - 02h sdram operation mode: for the bits [2:0], the operation modes are defined as follows: 3 ? b 000: normal sdram mode 3 ? b 001: nop command enable 3 ? b010 : precharge all banks 3 ? b 011: msr enable (mode register set enable) 3 ? b 100: cbr refresh cycle enable others: idle for power-up for the bit [3], it is called refresh_en , defined as follows: 0: turn off hardware refresh cycle (default) 1: turn on hardware refresh cycle after the last refresh operation issued by software in the initialization cycle, software should enable th e bit ? refresh_en ? immediately to notify sdram control module ? s dramctl ? to start gen e rating refresh cycle periodically. the initialization of sdram control module is illustrated as follows: sdramtype ? 0 : 16mb cl ? 1 : read latency = 2 (3) delay 1 s (4) rsdm ? 1 : nop (5) delay 1 s (6) rsdm ? 2 : precharge (7) delay 1 s (8) loop 7 times rsdm ? 4 : refresh delay 1 s rsdm ? 1 : nop delay 1 s (9) rsdm ? 0ch : refresh & turn on hardware refresh (10) delay 1 s (11) rsdm ? 0bh : mode register set enable (12) delay 1 s (13) rsdm ? 08h : normal sdram mode (14) end0a ? 0x04 : dim bank 0 ending address = 32mb (15) end1a ? 0x08 : dim bank 1 ending address = 64mb (16) end2a ? 0x0c : dim bank 2 ending address = 96mb (17) end3a ? 0x10 : dim bank 3 ending address = 128mb rsdm [3:0] 5 r/w 03h bits [27:23] of dim m bank 0 ending address for the case that there are two 32 mb sdram modules plugged in dimm slot 0 and two 16 mb sdram modules plugged in dimm slot 1, assign the registers as follows end0a = 0 4 h to indicate the ending address of dimm b ank 0 is at 2^2 5 ( 32 mb) end 1 a = 08h to indicate the ending address of dimm b ank 1 is at 2^2 6 ( 64 mb) end 2 a = 0ah to indicate the ending address of dimm b ank 0 is at 2^2 6+2^24 ( 80 mb) end 3 a = 0ch to indicate the ending address of dimm b ank 0 is at 2^2 6+2^25 ( 96 mb) end0a [4:0] 0 r/w 04h bits [27:23] of dim m bank 1 ending address (see end0a) end1a [4:0] 0 r/w 05h bits [27:23] of dim m bank 2 ending address (see end0a) end2a [4:0] 0 r/w 06h bits [27:23] of dim m bank 3 ending address (see end0a) end3a [4:0] 0 r/w
via technologies, inc. preliminary VT6516 datarsheet - 46 - 07h sdram command drive strength configure bit0: rdcsdv --- sdram chip select drive strength bit1: rmadv --- sdram ma drive strength ( including ras,cas,we,ma,ba) bit2: rmddv --- sdram md drive strength sdram_dr_ cfg [2:0] 0 r/w 08h sdram bank interleaving disable 0: enable interleaving (default) 1 : disable interleaving bk_il_dis [0] 0 r/w 4.2 registers of sram control module * base address: 0800h addres s (offset ) function register name bits defau lt value r/ w 00h sram read command interleave disable 0: enable interleaving (default) 1 : disable interleaving sram_read _il_dis [0] 0 r/w 4.3 registers of queue control module * base address: 0c00h addres s (offset ) function register name bits defau lt value r/ w 00- 02h free memory flow control threshold register as freemcnt(a register in buffer control) < fmfct, the congestion control function will be triggered to command the tmac module of the source port, destined to a congested port, to send out a flow control frame for full duplex mode, or to make back-pressure for half duplex mode. see the context about congestion control for details. larger the threshold value more sensitive the congestion control mechanism, i.e. maybe poor utilization for packet buffers but larger packet loss rate. smaller the threshold value less sensitive the congestion control mechanism, i.e. maybe good utilization for packet buffers but smaller packet loss rate. it depends on the network configuration and traffic pattern. the recommended threshold value is 256. fmfct [18:0 ] 0 r/ w 03h cut through enable 0: dis able cut through (default) 1: en able cut through note: remember to enable the cut-through function to improve the switching latency. for 100mbps input port, the smallest latency for cut-through is 288 bytes time (288x8x10 ns). for 10mbps input port, the smallest latency for cut-through is 96 bytes time (96x8x100 ns). cut_throu gh_en [0] 0 r/w
via technologies, inc. preliminary VT6516 datarsheet - 47 - 04h cpu port speed configuration 3 ? b 000: 1 mbit (default) 3 ? b 001: 5 mbit 3 ? b 010: 10 mbit 3 ? b 011: 20 mbit 3 ? b 100: 40 mbit 3 ? b 101: 50 mbit 3 ? b 110: 80 mbit 3 ? b 111: 100 mbit this register is used to calculate the congestion factor of the cpu port, that is the quotient of the accumulated byte count of the cpu output queue to the specified cpu port speed. while the congestion control is triggered, the output ports with congestion factor larger than the average will enter into the congestion control mode. cpu_spd_cf g [2:0] 0 r/w 10- 13h congestion factor of output port 0 the congestion factor, i.e. the quotient of the accumulated byte count of the output queue to the port speed, for each of 16 ethernet ports is calculated by the flow control module. while the congestion control is triggered, the output ports with congestion factor larger than the average will enter into the congestion control mode. congest_f ct0 [25:0] 0 r/o 14- 17h congestion factor of output port 1 congest_f ct1 [25:0] 0 r/o 18- 1bh congestion factor of output port 2 congest_f ct2 [25:0] 0 r/o 1c- 1fh congestion factor of output port 3 congest_f ct3 [25:0] 0 r/o 20- 23h congestion factor of output port 4 congest_f ct4 [25:0] 0 r/o 24- 27h congestion factor of output port 5 congest_f ct5 [25:0] 0 r/o 28- 2bh congestion factor of output port 6 congest_f ct6 [25:0] 0 r/o 2c- 2fh congestion factor of output port 7 congest_f ct7 [25:0] 0 r/o 30- 33h congestion factor of output port 8 congest_f ct8 [25:0] 0 r/o 34- 37h congestion factor of output port 9 congest_f ct9 [25:0] 0 r/o 38- 3bh congestion factor of output port 10 congest_f ct10 [25:0] 0 r/o 3c- 3fh congestion factor of output port 11 congest_f ct11 [25:0] 0 r/o 40- 43h congestion factor of output port 12 congest_f ct12 [25:0] 0 r/o 44- 47h congestion factor of output port 13 congest_f ct13 [25:0] 0 r/o 48- 4bh congestion factor of output port 14 congest_f ct14 [25:0] 0 r/o
via technologies, inc. preliminary VT6516 datarsheet - 48 - 4c- 4fh congestion factor of output port 15 congest_f ct15 [25:0] 0 r/o 50- 53h congestion factor of output port 16 (cpu port) there are 11 bits are used for reading freemcnt. only 15 bits are used as cpu port ? s congestion factor . the read sequence of congest_fct16[14:0] is as follows: 1. read 0c50h to get the lowest byte. congest16[7:0] = hd[7:0] 2. read 0c51h to get the other 7 bits. congest16[14:8] = hd[6:0] congest_f ct16 [25:0] 0 r/o 4.4 registers of buffer control module * base address: 1000h addres s (offset ) function register name bits defau lt value r/ w 00-02h bank 0 free pointer this register is initialized according to sdramtype while the cfp is written. for 16/64mbit sdram, its value is always 128 because the bank 0 free list follows the private buffer pool of buffer entries 0~127. the free buffers with starting address at the sdram even bank should be linked into this free list to improve the sdram bandwidth utilization. however, if the free buffers are misplaced, they will returned to the adequate free lists after their first release by the output port control. internally, the free pointer refers to the id of the 1st free buffer, rather than its physical address in sram (that is equal to id*3). free0_pt [18:0 ] r/o 03-05h bank 1 free pointer this register is initialized according to sdramtype while the cfp is written. for 16mbit sdram, its value is 130. for 64mbit sdram, its value is 131. the fixed buffer size is 1536 bytes. because the page size is 2kb for 16mbit sdram, the first public buffer of bank 1 is the 130th entry located at page 1. because the page size is 4kb for 64mbit sdram, the first public buffer of bank 1 is the 131 st entry located at page 1. free1_pt [18:0 ] r/o 06- 08h free memory block count it is an integer value < = sizeof(sdram) / 1.5kb . it has to be specified at the switch initialization stage. to fix the bug of reading freemcnt in vt3061a, the bit mapping for reading freemcnt is modified in vt3061b. the write sequence of freemcnt is also to write data to 1006h, 1007h, 1008h. however, the read sequence of freemcnt has to read data from ( 1 ) read 1006h to get the lowest byte, and also lock the counter information , .i.e. freemcnt[7:0] = hd[7:0] ( 2 ) read 0c52h to get the second byte , i.e. freemcnt[15:8] = hd[7:0] ( 3 ) read 0c53h to get the freemcnt[17:16] freemcnt[17:16] = hd[1:0] ( 4 ) read 0c51h to get the freemcnt[18] freemcnt[18] = hd[7] freemc nt [18:0 ] r/ w
via technologies, inc. preliminary VT6516 datarsheet - 49 - 09h clear all free pointers write to this register will reset the two free buffer pointers according to the sdramtype. it is the only way to program the free0_pt and free1_pt. this command should be taken after the sdramtype has been specified. cfp [0] w/ o 10h private memory allocation bit mask for port 0 each bit corresponds to a private packet buffer. this mask register will be cleared to bit pattern 0000 - 0000 while system reset . the 8 private buffers for the port k are that of entry ids (k*8) ~ (k*8+7). but, the cpu io port has not private buffers. port0_m ask [7:0] 0 r/o 11h private memory allocation bit mask for port 1 port1_m ask [7:0] 0 r/o 12h private memory allocation bit mask for port 2 port2_m ask [7:0] 0 r/o 13h private memory allocation bit mask for port 3 port3_m ask [7:0] 0 r/o 14h private memory allocation bit mask for port 4 port4_m ask [7:0] 0 r/o 15h private memory allocation bit mask for port 5 port5_m ask [7:0] 0 r/o 16h private memory allocation bit mask for port 6 port6_m ask [7:0] 0 r/o 17h private memory allocation bit mask for port 7 port7_m ask [7:0] 0 r/o 18h private memory allocation bit mask for port 8 port8_m ask [7:0] 0 r/o 19h private memory allocation bit mask for port 9 port9_m ask [7:0] 0 r/o 1ah private memory allocation bit mask for port 10 port10_ mask [7:0] 0 r/o 1bh private memory allocation bit mask for port 11 port11_ mask [7:0] 0 r/o 1ch private memory allocation bit mask for port 12 port12_ mask [7:0] 0 r/o 1dh private memory allocation bit mask for port 13 port13_ mask [7:0] 0 r/o 1eh private memory allocation bit mask for port 14 port14_ mask [7:0] 0 r/o 1fh private memory allocation bit mask for port 15 port15_ mask [7:0] 0 r/o 4.5 registers of forwarding control module
via technologies, inc. preliminary VT6516 datarsheet - 50 - * base address: 1400h addres s (offset ) function register name bits defau lt value r/ w 00h bits of mac address used as index for forwarding table 3 ? b000 : use mac address bit 10-0 (default) 3 ? b 001: use mac address bit 11-0 3 ? b 010: use mac address bit 12-0 3 ? b 011: use mac address bit 13-0 3 ? b 100: use mac address bit 14-0 others , use mac address bit 10-0 this register specifies the lookup hash key. for example, if the mac address bits [14:0] is used as the hash key, there must be 32k 96-byte table entries necessary to be allocated in the upper part of sram for destination mac lookup and source mac learning. hash_bits [2:0] 0 r/w 01- 03h starting sram address register for forwarding table base the forwarding table should be located above the linked buffer entries in the sram. the starting address of the forwarding table is specified by tbl_base in unit of 32-bit word. the occupied size is determined by hash_bits. for example, if there are maximum 5461 buffers entries used for 8mb sdram, the minimum forwarding table base is 5461*3 because each linked buffer entry is of size 96 bits (3 words). tbl_base [18:0] 0 r/w 04h user configured forwarding mode bit 0 ? if using the specified forwarding mask without lookup (default: 0, to take lookup without specified mask) bit 1 ? if not forwarding packets destined to congested ports (default: 0, not to filter packets by congestion factors) if fwd_mode[0] = 1, the incoming packets would not be forwarded with table lookup. however, the user_pm is used as the forwarding mask if the incoming packets are not from the cpu port. for broadcast & lookup-miss packets, the user_pm is returned by forwarding control to io control as the lookup result. if fwd_mode[1] = 1, the incoming packets would not be forwarded to the congested ports whose congestion factors are larger than 511. fwd_mode [1:0] 0 r/w 05- 07h user configured port mask the user_pm is used as the lookup result for the incoming packets from ethernet ports in the following cases: fwd_mode = 1 fwd_mode = 0, vlan is off, stp_state is ? forward ? , and this is a broadcast packet or a lookup-miss packet user_pm [16:0] 0 r/w 08- 09h port mask for packets sent by cpu the cpu_pm is used as the lookup result for the incoming packets from the cpu port without regard to packet ? s dmac. cpu_pm [15:0] 0 r/w
via technologies, inc. preliminary VT6516 datarsheet - 51 - 0ah cpu port related forwarding configuration bit 0 ? enable forward ing broadcast packet s with dmac=0xffffffffffff to cpu (default = 0 : disable) bit 1 ? enable forward ing spanning-tree packets to cpu (default = 0 : disable) bit 2 ? enable forward ing unicast packets with dmac = switch mac base to cpu (default = 0 : disable) the three register bits are used to enable/disable forwarding the above three types of frames to the cpu port. note that for a lookup-miss packet, whether it will be forwarded to the cpu port is determined by the bit user_pm[16], rather than this register. cpu_fwd_c fg [2:0] 0 r/w 0bh s niffer p ort id this register is valid only if monitor_pm is not all 0's. the default value of monitor_pm is all 0's to disable the sniffer function . sniffer_pid [3:0] 0 r/w 0c-0eh m onitor p ort m ask this register is used to specify which ports to be monitored by sniffer so that all packets forwarded from/to the monitored ports are also made a copy sent to the sniffer port. the sniffer function is enabled only if monitor_pm is not all 0's. the default value of monitor_pm is all 0's to disable the sniffer function . monitor_p m [16:0] 0 r/w 10h high byte [14:8] of the mac hash address to be aged age_mac is in the hash-key format of bits [14:0]. the high byte [14:8] is stored in the age_mac register of offset 10h. the low byte [7:0] is stored in the age_mac register of offset 11h. a write to the register of offset 11h will trigger an aging operation that decreases by one the age count of the corresponding forwarding table entry. a forwarding table entry with age count = 0 is an invalid entry, i.e. this entry is available for the source mac learning. age_mac is reset to all 0's after aging. age_mac [6:0] 0 r/w 11h low byte [7:0] of the mac hash address to be aged (see the above) age_mac [7:0] 0 r/w 12h a ging s tatus 0, idle or done (default) 1: aging in progress after an aging command is issued, the status is recorded in this register. the next age command can only be issued as the status changes from 1 (in-progress) to 0 (done). aging_stat us [0] 0 r/o
via technologies, inc. preliminary VT6516 datarsheet - 52 - 20h spanning tree state for port 0 2 ? b 00 ? blocki n g state (default) 2 ? b 01 ? listening state 2 ? b 10 - learning state 2 ? b 11 ? forwarding state the forwarding operation in each ethernet port is controlled by its associated spanning tree state. in blocking or listening state, the incoming packets will not trigger any dmac lookup operation and smac learning operation. in learning state, the incoming packets will not trigger dmac lookup operation, but the smac learning operation will be triggered for crc-ok packets. only in forwarding state, an incoming packet will trigger dmac lookup operation while the first 24 bytes are received, and it will trigger the smac learning operation while the whole packet is received with good crc. for the 802.1d spanning tree algorithm, a blocked port for loop avoidance should enter the blocking state so that any incoming packets are filtered without forward. a normal port that does not cause any loop should be in the forwarding state. port0_stp_ state [1:0] 0 r/w 21h spanning tree state for port 1 port1_stp_ state [1:0] 0 r/w 22h spanning tree state for port 2 port2_stp_ state [1:0] 0 r/w 23h spanning tree state for port 3 port3_stp_ state [1:0] 0 r/w 24h spanning tree state for port 4 port4_stp_ state [1:0] 0 r/w 25h spanning tree state for port 5 port5_stp_ state [1:0] 0 r/w 26h spanning tree state for port 6 port6_stp_ state [1:0] 0 r/w 27h spanning tree state for port 7 port7_stp_ state [1:0] 0 r/w 28h spanning tree state for port 8 port8_stp_ state [1:0] 0 r/w 29h spanning tree state for port 9 port9_stp_ state [1:0] 0 r/w 2ah spanning tree state for port 10 port10_stp _state [1:0] 0 r/w 2bh spanning tree state for port 11 port11_stp _state [1:0] 0 r/w 2ch spanning tree state for port 12 port12_stp _state [1:0] 0 r/w 2dh spanning tree state for port 13 port13_stp _state [1:0] 0 r/w 2eh spanning tree state for port 14 port14_stp _state [1:0] 0 r/w 2fh spanning tree state for port 15 port15_stp _state [1:0] 0 r/w 80h port 0 vlan id the vlan feature is enabled only when a ll port vid's are configured to a valid (non-zero) vid. port0_vid [5:0] 0 r/w 82h port 1 vlan id port1_vid [5:0] 0 r/w 84h port 2 vlan id port2_vid [5:0] 0 r/w 86h port 3 vlan id port3_vid [5:0] 0 r/w 88h port 4 vlan id port4_vid [5:0] 0 r/w
via technologies, inc. preliminary VT6516 datarsheet - 53 - 8ah port 5 vlan id port5_vid [5:0] 0 r/w 8ch port 6 vlan id port6_vid [5:0] 0 r/w 8eh port 7 vlan id port7_vid [5:0] 0 r/w 90h port 8 vlan id port8_vid [5:0] 0 r/w 92h port 9 vlan id port9_vid [5:0] 0 r/w 94h port 10 vlan id port10_vid [5:0] 0 r/w 96h port 11 vlan id port11_vid [5:0] 0 r/w 98h port 12 vlan id port12_vid [5:0] 0 r/w 9ah port 13 vlan id port13_vid [5:0] 0 r/w 9ch port 14 vlan id port14_vid [5:0] 0 r/w 9eh port 15 vlan id port15_vid [5:0] 0 r/w a0- a1h server p ort m ask the srv_pm is used only when vlan is enabled. as the vlan feature is enabled (i.e. all port vid ? s are valid (non-zero)), the behavior is described for the following scenarios: a broadcast or lookup-miss packet will be forwarded to the ports of same vlan id. if cpu_fwd_cfg[0]=1, the broadcast packet will also be forwarded to cpu port. a unicast packet destined to different vlan will be forwarded to cpu port if vlan_fwd_cfg[0]=1. a unicast packet destined to another port in the same vlan will be forwarded in a unicast manner. the srv_pm should be set for the server ports that respond to carry cross vlan packets. it is recommended that all packets from the server stations have not any embedded vid. only the cross vlan packets through the server ports (the corresponding srv_pm bits are on) within different vlan domain must carry vid. in the source-mac learning procedure, for packets with tagged vid, the corresponding forwarding table entry will have not the tagging bit on to make the outgoing packets destined to it with vid tagged. all valid forwarding table entries should have non-zero vid. srv_pm [15:0] 0 r/w a2h vlan related forwarding configuration this register bit is used to enable those packets destined to a different vlan also to be forwarded to the cpu port . this scenario happens when the following conditions hold simultaneously : t he destination mac address is found in forwarding table (lookup hit), and this entry is not static. note that if the entry is static, its priority is highest and the destination ports are fully determined by the port mask field in the entry so that forwarding to cpu is not necessary. the source vid differs from the destination vid . vlan_fwd_ cfg [0] 0 r/w 4.6 registers of phy control module * base address: 1800h
via technologies, inc. preliminary VT6516 datarsheet - 54 - addres s (offset ) function register name bits defau lt value r/ w 00h phy id this is used to specify which phy device is the objective of the following mii commands. there are maximum 16 rmii phy devices. phyid [3:0] 0 w/ o 01h phy register address in each phy device, there are maximum 32 mii management registers accessible by the cpu. the phy_reg_addr register is used to specify which one is the objective of the following access command. phy_reg _addr [4:0] 0 w/ o 02- 03h phy data register each phy management register is 16 bits. every data access to a phy management register is in unit of 16 bits, stored in this register. phydat a [15:0 ] r/ w 04h phy command register 1: read 0: write write 0 to this register will cause a write operation to the phy management register (specified by the phy_reg_addr) of the phy device (specified by the phyid). write 1 to this register will cause a read operation. a read or write operation takes about 0.4 ms so that the cpu has to read the physts register periodically to check if the issued command is complete. phycmd [0] w/ o 05h phy status register 2 ? b 00: idle 2 ? b 01: busy 2 ? b 10: complete this register indicates the status of the phy control module. initially, the phy control module is in the idle status. while a read or write command is issued by writing 1/0 to the phycmd register, physts becomes ? busy ? immediately, and goes into the ? complete ? status as this operation finishes. then, a following ? read status ? command will cause it back to the ? idle ? status, or a following read/write command will cause it into the ? busy ? status. physts [1:0] 0 r/o 10h port0 phy device address the pair of 5-bit phy device address and 5-bit register address forms a unique access address to a phy device ? s register. each phy device has a unique device address that is identified by the phyid. in the system initialization, the cpu should write phy device addresses, corresponding to every phy devices, to registers port[0..15]_phy_addr, that may be recorded in the eeprom or code rom. port0_p hy_add r [4:0] 0 r/ w 11h port1 phy device address port1_p hy_add r [4:0] 0 r/ w 12h port2 phy device address port2_p hy_add r [4:0] 0 r/ w
via technologies, inc. preliminary VT6516 datarsheet - 55 - 13h port3 phy device address port3_p hy_add r [4:0] 0 r/ w 14h port4 phy device address port4_p hy_add r [4:0] 0 r/ w 15h port5 phy device address port5_p hy_add r [4:0] 0 r/ w 16h port6 phy device address port6_p hy_add r [4:0] 0 r/ w 17h port7 phy device address port7_p hy_add r [4:0] 0 r/ w 18h port8 phy device address port8_p hy_add r [4:0] 0 r/ w 19h port9 phy device address port9_p hy_add r [4:0] 0 r/ w 1ah port10 phy device address port10_p hy_add r [4:0] 0 r/ w 1bh port11 phy device address port11_p hy_add r [4:0] 0 r/ w 1ch port12 phy device address port12_p hy_add r [4:0] 0 r/ w 1dh port13 phy device address port13_p hy_add r [4:0] 0 r/ w 1eh port14 phy device address port14_p hy_add r [4:0] 0 r/ w 1fh port15 phy device address port15_p hy_add r [4:0] 0 r/ w 4.7 registers of eeprom control module * base address: 1c00h
via technologies, inc. preliminary VT6516 datarsheet - 56 - addres s (offset ) function register name bits defau lt value r/ w 00h eeprom word address for a 256-byte eeprom device, an 8-bit data object is identified with this register. for a 512-byte eeprom device, an 8-bit data object is identified with this register plus eedevaddr[1]. for a 1024-byte eeprom device, an 8-bit data object is identified with this register plus eedevaddr[2:1], vice versa. eewdad dr [7:0] w/ o 01h eeprom data every data access to eeprom is in unit of 8 bits, stored in this register. eedata [7:0] r/ w 02h eeprom device address bit 7-4 : device type id (eeprom 1010) bit 3-1 : device id bit 0 : r/w command , value 0: write ; value 1: read the triple of 4-bit phy device type id, 3-bit device id, and 7-bit word address forms a unique access address to an 8-bit eeprom data object. this register ? s bit 0 is used to specify the command type: 0 for write and 1 for read. a read or write operation takes about 0.4 ms so that the cpu has to read the eeysts register periodically to check if the issued command is ? complete without error ? or ? ack error ? . eedeva ddr [7:0] w/ o 03h eeprom status register 3 ? b 000: idle 3 ? b 001: busy 3 ? b 010: complete with out error 3 ? b 100: ack error this register indicates the status of the eeprom control module. initially, the eeprom control module is in the idle status. while a read or write command is issued by writing 1/0 to eedevaddr[0], eests becomes ? busy ? immediately, and goes into the ? complete ? status as this operation finishes or into the ? ack error ? as an acknowledge error happens. then, a following ? read status ? command will cause it back to the ? idle ? status, or a following read/write command will cause it into the ? busy ? status. eests [2:0] r/o 4.8 registers of cpu interface module * base address: 2000h addres s (offset ) function register name bits defau lt value r/ w
via technologies, inc. preliminary VT6516 datarsheet - 57 - 00h interrupt status register bit 0 : interrupt indication for read / write phy command complete bit 1 : interrupt indication for read / write eeprom command complete or error bit 2 : interrupt indication for cpu io port receiving an incoming packet bit 3 : interrupt indication for cpu io port finishing the transmission of an outgoing packet t o clear an interrupt, write 1 to the corresponding irqsts bit. however, write 0 will not cause any change on that interrupt. irqsts [3:0] 0 r/ w 01h- 03h sram address register the data object addressed is in unit of 32 bits. the max imum allowable sram size is 1mb. for sram direct access, the cpu has to (1) set sramaddr & sramdata, (2) issue read/write command by sramcmd, and (3) check command status by sramsts. sramad dr [18:0 ] r/ w 04h- 07h sram data register sramda ta [31:0 ] r/ w 08h sram command register 2 ? b 00 : n op 2 ? b 01 : read 2 ? b 10 : write to make a direct read to sram, write sramcmd by 2 ? b01. to make a direct write to sram, write sramcmd by 2 ? b10. read/write will cause the sramsts = ? busy ? immediately. as it is done, sramsts = ? done ? . a following read to sramsts will clear it to ? idle ? . sramcm d [1:0] r/ w 09h sram status register 2 ? b 01 : read /write command done 2 ? b 10 : busy (read/write in progress) 2 ? b 00 : idle sramsts [1:0] 0 r/o 10h- 13h sdram address register the data object addressed is in unit of 64 bits. the max imum allowable sdram size is 128 mb. for sdram direct access, the cpu has to (1) set sdramaddr & sdramdata, (2) issue read/write command by sdramcmd, and (3) check command status by sdramsts. sdrama ddr [23:0 ] r/ w 14h- 1bh sdram data register sdramd ata [63:0 ] r/ w 1ch sdram command register 2 ? b 00 : n op 2 ? b 01 : read 2 ? b 10 : write to make a direct read to sdram, write sdramcmd by 2 ? b01. to make a direct write to sdram, write sdramcmd by 2 ? b10. read/write will cause the sdramsts = ? busy ? immediately. as it is done, sdramsts = ? done ? . a following read to sdramsts will clear it to ? idle ? . sdramc md [1:0] r/ w 1dh sdram status register 2 ? b 01 : read /write command done 2 ? b 10 : busy (read/write in progress) 2 ? b 00 : idle sdrams ts [1:0] 0 r/o
via technologies, inc. preliminary VT6516 datarsheet - 58 - 20h write packet command 3 ? b100 : end of frame with the remaining data size = 2 bytes 3 ? b101 : end of frame with the remaining data size = 1 byte (that is the low byte as using 16-bit write) 3 ? b000 : idle 3 ? b001 : start of frame for the next write 3 ? b010 : middle of frame for the next write 3 ? b011 : abort the unfinished packet write cpu should write this command register before repeatedly writ ing 8/ 16 bit packet data via the isa/ ide bus (with a2, a1, a0 = 000). wr_pkt_ cmd [2:0] w/ o 21h packet abort write this register to drop an incoming packet ready to be read by cpu. err_abo rt [0] w/ o 30h bits [47:40] of switch base mac address [47:0] each port in the switch ic has a unique mac address with the port id as address bits [3:0] and the same mac base bits [47:4], specified by the register switch_mac_base[47:4]. switch_ mac_ba se [7:0] 0 r/ w 31h bits [39:32] of switch base mac address [47:0] switch_ mac_ba se [7:0] 0 r/ w 32h bits [31:24] of switch base mac address [47:0] switch_ mac_ba se [7:0] 0 r/ w 33h bits [23:16] of switch base mac address [47:0] switch_ mac_ba se [7:0] 0 r/ w 34h bits [15:8] of switch base mac address [47:0] switch_ mac_ba se [7:0] 0 r/ w 35h bits [7:4] of switch base mac address [47:0] switch_ mac_ba se [7:4] 0 r/ w 40h interrupt mask register bit 0 : phy interrupt mask bit 1 : eeprom interrupt mask bit 2 : packet received interrupt mask bit 3 : packet sent interrupt mask the four interrupts can be masked individually. the value 0 indicates ? masked ? , and value 1 (default) indicates ? unm asked ? . irqsts_ mask [3:0] 4 ? b11 11 r/ w
via technologies, inc. preliminary VT6516 datarsheet - 59 - 50h cpu soft reset for the whole switch chip reset for read 0: soft reset in progress 1: soft reset done for write, any value will trigger the whole chip reset the soft reset is similar to power-on reset for the switch chip, except that it is asserted by writing any value to this register. the cpu soft reset has to take 16 rclk50 cycle s, i.e. 320ns , to make the switch chip being reset and ready to cpu . for 8mhz 8051 cpu that an instruction cycle is 1.5 s, it need s to wait for 4 cpu instruction cycles to continue after the soft reset . or, cpu can read this register cpu_soft_reset until value 1 is returned. note that reading this register will not cause the address register to increment automatically. so, consecutively reading from 2050h to 2051h should not be applied. that is, any reading to 2051h has to specify the address explicitly. cpu_sof t_reset [0] 1 r/ w 51h revision id register this register is used to record the revision code. its value is 0 for the first sample ics. revisio n_id [7:0] 0 r/o 4.9 registers of mac/io control module * base address: 2400h addres s (offset ) function register name bits defau lt value r/ w 00h configurable preamble bytes this register specifies the preamble length (0..7 bytes) for outgoing packets. pream_c fg [2:0] 7 r/ w
via technologies, inc. preliminary VT6516 datarsheet - 60 - 01h configurable frame gap in di bits for 1st interval this register specifies the 1 st interval of the inter-frame gap (in unit of di bit) for outgoing packets, where the 2 nd interval of the inter- frame gap is fixed as 16 di bits (i.e. 32 bits). the minimum inter- frame gate (ifg) defined in 802.3 is 96 bits (48 di bits). but for fast transmission, many manufactures use smaller ifg (minimum is 32 bits) in practical. the allowable ifg_cfg value is 0..63 di bits. note that, tmac only performs the carrier sense function during the 1 st ifg interval, rather than the whole ifg. so, for the half duplex link, if an incoming packet arrives at the 2 nd ifg interval, a collision with the ready-to-send outgoing packet will happen. ifg_cfg [5:0] 32 r/ w
via technologies, inc. preliminary VT6516 datarsheet - 61 - 02h backoff configuration bit 0: cap mode , mild solution for capture effect bit 1: mba mode , aggressive solution for capture effect bit 2: eefast mode , drop the 2 nd collided packet for testing purpose, accelerate the drop event bit 3: crandom mode , use another random algorithm bit 4: ofset , parameter for backoff timer for that cap mode is enabled, the tmac module will select the backoff time as b ? 10 or b ? 11 for the 2 nd collision , i.e. the backoff time for the 2 nd collision is 2 or 3 slot times, where a slot time is 512 bits time duration. for that mba mode is enabled, the tmac will select backoff time for 10 th collision just as that for 5 th collision backoff time for 11 th collision just as that for 4 th collision backoff time for 12 th collision just as that for 3 rd collision backoff time for 13 th collision just as that for 2 nd collision backoff time for 14 th collision just as that for 1 st collision backoff time for 15 th collision as 0. for that eefast mode is enabled, the output control will drop the packet immediately as the second collision happens. for that crandom mode is enabled, the tmac will select the backoff time by using the alternative random algorithm that calculates the backoff time as that for 10 th collision. for ofset=1, the tmac will follow the 802.3 standard backoff algorithm. for ofset=0, the tmac will select the backoff time for the 1 st and 2 nd collision as that of the 3 rd collision, i.e. the possible the backoff time for the 1 st and 2 nd collision is ranged from 0 to 7 in unit of slot time. boffcfg [4:0] 5 ? b10 000 r/ w
via technologies, inc. preliminary VT6516 datarsheet - 62 - 03h mac media type configuration bit 0: spd_10m , value 0: 100mb ps, value 1: 10mb ps bit 1: half_dpx , 1: half duplex, 0: full duplex bit 2: rcv_fc_dis , 1 : disable receive flow control frame 0: en able receive flow control frame bit 3: xmt_fc_dis , 1 : disable send flow control frame 0: en able send flow control frame maccfg [3:0] 0 r/ w 04h io port enable bit 0: input port enable , 1 : input enable, 0 : input disable bit 1: output port enable , 1 : output enable, 0 : output disable io_cfg [1:0] 0 r/ w 10h- 13h received good packet count accounting e vent: receiving packets with crc ok and packet size between 64 and 1522 (valid maximum packet size in spite of vlan disabled or enabled) . note that the rmon/mib counter will be locked during 4-byte continuous register-read, and the increment (if any) is deferred until read complete. rcv_go od_pkt [31:0 ] 0 r/o 14h- 17h received bad packet count formal definition: "the number of inbound packets that contained errors preventing them from being deliverable to a higher-layer protocol." accounting e vents: (1) receiving valid-length packets with crc error, (2) receiving runt packets, (3) receiving over- length packets rcv_bad _pkt [31:0 ] 0 r/o 18h- 1bh drop packet counter formal definition: "the total number of events in which packets were dropped by the probe due to lack of resources. note that this number is not necessarily the number of packets dropped; it is just the number of times this condition has been detected." accounting e vent: input fifo overrun due to sdram-bandwidth blocking or buffer starvation. drop_pk t [31:0 ] 0 r/o 1ch- 1fh sent good packet count accounting e vent: store-and-forward transmission success without collision xmt_go od_pkt [31:0 ] 0 r/o
via technologies, inc. preliminary VT6516 datarsheet - 63 - 20h- 23h sent bad packet counter formal definition: "the number of outbound packets that could not be transmitted because of errors." accounting e vent: re-transmission due to collision or output fifo underrun . xmt_ba d_pkt [31:0 ] 0 r/o 2800h mac & i/o control module of port 1 as same as port 0 2c00 h mac & i/o control module of port 2 as same as port 0 3000h mac & i/o control module of port 3 as same as port 0 3400h mac & i/o control module of port 4 as same as port 0 3800h mac & i/o control module of port 5 as same as port 0 3c00 h mac & i/o control module of port 6 as same as port 0 4000h mac & i/o control module of port 7 as same as port 0 4400h mac & i/o control module of port 8 as same as port 0 4800h mac & i/o control module of port 9 as same as port 0 4c00 h mac & i/o control module of port 10 as same as port 0 5000h mac & i/o control module of port 11 as same as port 0 5400h mac & i/o control module of port 12 as same as port 0 5800h mac & i/o control module of port 13 as same as port 0 5c00 h mac & i/o control module of port 14 as same as port 0 6000h mac & i/o control module of port 15 as same as port 0 4.10 registers of cpu io control module * base address: 6400h addres s (offset ) function register name bits defau lt value r/ w 00h cpu packet read byte count register bits [7:0] cpu can check the incoming packet length via the 11-bit register pkt_byte_cnt [10:0] before starting to read it. pkt_byt e_cnt [7:0] 0 r/o 01h cpu packet read byte count register bits [10:8] pkt_byt e_cnt [10:8 ] 0 r/o
via technologies, inc. preliminary VT6516 datarsheet - 64 - 02h cpu packet read status register 2 ? b00: idle or packet read in progress 2 ? b01: packet received successfully 2 ? b10: packet received with error (cpu needs to read the same packet again) rd_pkt_ status [1:0] 0 r/o 03h packet source port id cpu can check the incoming packet ? s source port id via the 3-bit register pkt_src_port before starting to read it. it is useful to the spanning tree algorithm. pkt_src _port [3:0] 0 r/o 04h cpu io port configuration register bit 0 : input port enable , 1 : input enable, 0 : input disable bit 1 : output port enable , 1 : output enable, 0 : output disable cpuio_c fg [1:0] 0 r/ w 10h cpu packet write status register bits [1:0] : packet write status 2 ? b00: idle or packet write in progress 2 ? b01: cpu sent packet successfully 2 ? b10: cpu sent packet un successfully (cpu needs to re-write the packet again) bit 2: cpu input control is ready for cpu to write packet s (it can be ready only after setting cpuio_cfg[0] = 1.) 0: not ready (default) 1: ready wr_pkt_ status [2:0] 0 r/o
via technologies, inc. preliminary VT6516 datarsheet - 65 - s ection iii e lectrical s pecifications a bsolute m aximum r atings parameter min max unit ambient operating temperature 0 70 o c case temperature 0 100 o c storage temperature -55 125 o c input voltage -0.5 5.5 volts output voltage (v cc = 3.1 - 3.6v) -0.5 v cc + 0.5 volts note: stress above the conditions listed may cause permanent damage to the device. functional operation of this device should be restricted to the conditions described under operating conditions. dc c haracteristics ta-0-70 o c, v cc =3.3v+/-5%, gnd=0v symbol parameter min max unit condition v il input low voltage -0.50 0.8 v v ih input high voltage 2.0 v cc +0.5 v v ol output low voltage - 0.45 v i ol =4.0ma v oh output high voltage 2.4 - v i oh =-1.0ma i il input leakage current - +/-10 ua 0 via technologies, inc. preliminary VT6516 datarsheet - 66 - - cpu interface io timing characteristics symbol description min max unit t iorh , t iowh ior/iow falling to ior/iow rising 70 - ns t iorl , t iowl ior/iow rising to ior/iow falling 25 - ns t val hd valid to ior/iow falling 25 - ns t iows iow data setup(write data valid to iow rising) 20 - ns t iowh iow data hold(iow rising to write data invalid) 10 - ns t iors ior data setup(read data valid to ior rising) 20 - ns t iorh ior data hold(iow rising to read data invalid) 5 - ns ior hhhhhhhhfllllllllllrhhhhhfll ~ t iorh !~ t iorl ! ~ t val ! ~ t iors !~ t iorh ! hd zzzzznddddddddddddddddozzzzz cpu read timing diagram iowhhhhhhhhfllllllllllrhhhhhfll ~ t iowh !~ t iowl ! ~ t val ! ~ t iows !~ t iowh ! hd zzzzznddddddddddddddddozzzzz cpu write timing diagram
via technologies, inc. preliminary VT6516 datarsheet - 67 - - sram interface timing characteristics symbol description setup hold min max unit t sa sa output delay 2 7 ns t sds , t sdh sd input 2.5 1.5 ns t sd sd output delay 2 7 ns t sads sads output delay 2 7 ns t scs scs0 output delay 2 7 ns t swe swe output delay 2 7 ns sclk llrhhhhfllllrhhhhfllllrhhhflllrhhh + t sads ~ sads zzzzzndddddddddozzzzzzzzznddddddd + t scs ~ scs zzzzzndddddddddozzzzzzzzznddddddd + t swe ~ swe zzzzzndddddddddozzzzzzzzznddddddd + t sa ~ sa zzzzndddddddddozzzzzzzzznddddddd v input cycle v turn around cycle v output cycle v + t sds ~ \\ + t sd ~ sd nddddozzzzzzzzzzzzzzzzzznddddddo + t sdh ~
via technologies, inc. preliminary VT6516 datarsheet - 68 - - dram interface timing characteristics symbol description setup hold min max t ma ma output delay 2 6.5 t mds , t mdh md input 1.5 2 t m d md output delay 2 6.5 t ba ba0, ba1 output delay 2 6.5 t ras ras0, ras1 output delay 2 6.5 t cas cas0, cas1 output delay 2 6.5 t dw e dwe0, dwe1 output delay 2 6.5 t dcs dcs3~0 output delay 2 6 dclk llrhhhhfllllrhhhhfllllrhhhflllrhh + t ba ~ ba zzzzzndddddddddozzzzzzzzznddddddd + t ra s ~ ras zzzzzndddddddddozzzzzzzzznddddddd + t cas ~ cas zzzzzndddddddddozzzzzzzzznddddddd + t d w e ~ dwe zzzzzndddddddddozzzzzzzzznddddddd + t dcs ~ dcs zzzzzndddddddddozzzzzzzzznddddddd + t ma ~ ma zzzzndddddddddozzzzzzzzznddddddd v input cycle v turn around cycle v output cycle v + t mds ~ \\ + t md ~ md nddddozzzzzzzzzzzzzzzzzznddddddo + t ndh ~
via technologies, inc. preliminary VT6516 datarsheet - 69 - - rmii interface timing characteristics symbol description min type max unit condition t r c rclk50 cycle time 20 ns t rxds rxd crs_dv setup time 4 - - ns to rclk50 rising edge t rxdh rxd crs_dv hold time 2 - - ns to rclk50 rising edge t txd txd tx_en output delay 3 - 12 ns to rclk50 rising edge rclk lllrhhhhfllllrhhhhfllllrhhhhflll + t rxds ~ \\ crs_dvndddddozzzndddddozzznddddddozzzz + t rxdh ~ + t rxds ~ \\ rxd ndddddozzzndddddozzznddddddozzzz + t rxdh ~ + t txd ~ tx_en zzzzzndddddddddozzzzzzzzzznddddd + t txd ~ txd zzzzzndddddddddozzzzzzzzzznddddd
via technologies, inc. preliminary VT6516 datarsheet - 70 - mii interface timing characteristics symbol description min type max unit condition t r c rclk cycle time - 40 - ns t rxds rxd, rxdv setup time 5 - - ns to rclk50 rising edge t rxdh rxd, rxdv hold time 5 - - ns to rclk50 rising edge t tc tclk cycle time - 40 - ns t txd txd, tx_en output delay 4 - 20 ns to rclk50 rising edge - rclk lllrhhhhfllllrhhhhfllllrhhhhflll + t rxds ~ \\ crs_dvndddddozzzndddddozzznddddddozzzz + t rxdh ~ + t rxds ~ \\ rxd ndddddozzzndddddozzznddddddozzzz + t rxdh ~ tclk lllrhhhhfllllrhhhhfllllrhhhhflll + t txd ~ tx_en zzzzzndddddddddozzzzzzzzzznddddd + t txd ~ txd zzzzzndddddddddozzzzzzzzzznddddd - management interface (mi) timing characteristics parameter min typ max unit condition mdc cycle time - 400 - ns mdc high time 180 200 220 ns mdc low time 180 200 220 ns mdio setup time (source by phy) 30 - - ns to mdc rising edge mdio hold time (source by phy) 0 - - ns to mdc rising edge mdio output 200 - 300 ns to mdc rising
via technologies, inc. preliminary VT6516 datarsheet - 71 - delay (source by vt3061) edge
via technologies, inc. preliminary VT6516 datarsheet - 72 - - eeprom interface timing characteristics parameter min typ max unit condition eec clock frequency 0 78.12 - khz clock high time - 6.4 - m s clock low time - 6.4 - m s start condition setup time 6.4 - - m s start condition hold time 6.4 - - m s stop condition setup time 6.4 - - m s stop condition hold time 6.4 - - m s read data in setup time 0 - - to eec rising edge read data in hold time 0 - - to eec falling edge eeio data out delay 2.6 - 3.0 m s to eec falling edge write cycle time - 11.4 - ms
via technologies, inc. preliminary VT6516 datarsheet - 73 - p ackage m echanical s pecifications

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